Hello, I am running a back-annotated timing simulation with Modelsim, on the post-placement&routing VHDL code generated by ISE(Xilinx tool). This VHDL code does not have the initial design signal names or structures, as it comprises only by device-specific components instantiations. This makes debugging very hard.
Does anyone know how I can find the correspondance between initial signals' names and post-routed signals? Does ISE provide this information? Thank you in advance Giorgos P. --~--~---------~--~----~------------~-------~--~----~ You received this message because you are subscribed to the Google Groups "CDAC_PGDEVD_10" group. To post to this group, send email to [email protected] To unsubscribe from this group, send email to [EMAIL PROTECTED] For more options, visit this group at http://groups.google.co.in/group/CDAC_PGDEVD_10?hl=en -~----------~----~----~----~------~----~------~--~---
