On 30 Aug, 2014, at 8:19 pm, Aaron Wood wrote:

> Do you think this is a limitation of MIPS as a whole, or just the particular 
> MIPS cores in use on these platforms?  

There were historically a great many MIPS designs.  Several of the high-end 
designs were 64-bit and used in famous workstations.  The one we see in CPE 
today, however, is the MIPS equivalent of the AMD Geode, based on an old 
version of the MIPS architecture, and further crippled by embedded-style 
hardware choices.  It would have been a good CPU in 1989, considering that it 
would have competed against the 486 in the PC space, but it wouldn't have been 
hobbled by a 16-bit memory bus back then.

I'm not sure how much effort is going into improving the embeddable versions of 
MIPS cores, but certainly ARM seems to be a more active participant in the 
embedded space.  Their current range of embeddable cores scales from the 
Cortex-M0 (whose chief selling point is that it takes only a fraction of a 
square millimetre of die space) to some quite decent 64-bit multicore CPUs 
(which AMD is developing a server platform for), with a number of intermediate 
points along that continuum catered for.

So if a particular core works but proves to have inadequate performance, a 
better one can be integrated into the next version of the hardware, without any 
risk of having to rewrite all the software.  That future-proofing is probably 
important to manufacturers, and isn't very obviously available with MIPS cores.

I wouldn't be surprised to see something like a Cortex-A5, or possibly even a 
multicore Cortex-A7 in CPE.  These are capable of running conventional 
multitasking OSes like Linux (and hence OpenWRT), and have a lot of 
fully-mature toolchain support.  But perhaps they would leave out the FPU, or 
configure only the most basic type of FPU (VFPv3-D16), to save money compared 
to the NEON unit you'd normally find in a smartphone.

 - Jonathan Morton

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