These are ASICs, not fpgas. Presumably they are manufactured on Intel fabs using Intel processes, after designing them. The overview references RTL design specs. Now Verilog and VHDL can speciry RTL designs (but are a bit more general). Also, the I/O pins seem to be a bit more specialized than those of FPGAs I use from Xilinx. A typical FPGA has a fixed number of specialized I/O pins that can do very fast SERDES, for example. But I presume that these ASICs can have varying numbers of specialized I/O's. What typically distinguishes FPGAs, MCUs and ASICs from general purpose CPU chips is the I/O pins' potential configurability at design time. General purpose CPUs don't have GPIO or configurable specialized I/O. They typically dedicate each pin to a particular electrical bus signaling physical layer. In contrast, look at the STM32 or the RP2040 chips I/O pin specs. Configurability from input to output to differential from voltage to voltage on each single pin. These are things that software guys don't understand are important. And they aren't that important compared to logic and memory in general purpose CPUs like the X86 or the ARM general purpose chips. On Monday, March 1, 2021 10:10pm, "Dave Taht" <[email protected]> said:
> Got no idea how these really differ from fpgas. Do like the number of > gates tho. quad core 64bit arm also. Anyone seen the design tools? > > https://www.intel.com/content/www/us/en/products/programmable/asic/easic-devices/n5x.html > > -- > "For a successful technology, reality must take precedence over public > relations, for Mother Nature cannot be fooled" - Richard Feynman > > [email protected] <Dave Täht> CTO, TekLibre, LLC Tel: 1-831-435-0729 > _______________________________________________ > Cerowrt-devel mailing list > [email protected] > https://lists.bufferbloat.net/listinfo/cerowrt-devel >
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