[clang] [llvm] [RISCV] Add SiFive X390 processor definition (PR #142517)

[Min-Yih Hsu via cfe-commits]

================
@@ -290,7 +290,51 @@ def SIFIVE_X280 : RISCVProcessorModel<"sifive-x280", 
SiFive7Model,
                                        FeatureStdExtZvfh,
                                        FeatureStdExtZba,
                                        FeatureStdExtZbb],
-                                      SiFiveX280TuneFeatures>;
+                                      SiFiveIntelligenceTuneFeatures>;
+
+def SIFIVE_X390 : RISCVProcessorModel<"sifive-x390", NoSchedModel,
+                                      [Feature64Bit,
----------------
mshockwave wrote:

Unfortunately it lacks Zicclsm (misaligned load/store), which is part of 
RVA20U64 and subsequent profiles.

https://github.com/llvm/llvm-project/pull/142517
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