================
@@ -23146,10 +23152,24 @@
RISCVTargetLowering::getRegForInlineAsmConstraint(const TargetRegisterInfo *TRI,
&RISCV::VRN2M4NoV0RegClass}) {
if (TRI->isTypeLegalForClass(*RC, VT.SimpleTy))
return std::make_pair(0U, RC);
+
+ if (VT.isFixedLengthVector() && Subtarget.useRVVForFixedLengthVectors())
{
+ MVT ContainerVT = getContainerForFixedLengthVector(VT);
+ if (TRI->isTypeLegalForClass(*RC, ContainerVT))
+ return std::make_pair(0U, RC);
+ }
}
} else if (Constraint == "vm") {
if (TRI->isTypeLegalForClass(RISCV::VMV0RegClass, VT.SimpleTy))
return std::make_pair(0U, &RISCV::VMV0RegClass);
+
+ if (VT.isFixedLengthVector() && Subtarget.useRVVForFixedLengthVectors()) {
+ MVT ContainerVT = getContainerForFixedLengthVector(VT);
+ // VT here is coerced to vector with i8 elements, so we need to check if
----------------
topperc wrote:
I don't understand this comment. Where is it coerced?
https://github.com/llvm/llvm-project/pull/150724
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