================
@@ -186,9 +186,7 @@ def APSR : ARMReg<15, "apsr">;
def APSR_NZCV : ARMReg<15, "apsr_nzcv">;
def SPSR : ARMReg<2, "spsr">;
def FPSCR : ARMReg<3, "fpscr">;
-def FPSCR_NZCV : ARMReg<3, "fpscr_nzcv"> {
- let Aliases = [FPSCR];
----------------
davemgreen wrote:
Can we really say this doesn't alias FPSCR? If we set fpscr_nzcv it will set
bits of fpscr and vice-versa. The exception status bits (and the rounding
controls) are separate from nzcv, but that might not be the only use of the
register.
https://github.com/llvm/llvm-project/pull/137101
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