================
@@ -0,0 +1,939 @@
+; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
UTC_ARGS: --version 5
+; Test Flag Output Operands with 14 combinations of CCMASK and optimizations
+; for AND for 3 three different functions, including two tests from heiko.
+; This test checks combinations of EQUAL(==) and NOT EQUAL (!=) operator. e.g.
+; CC == 0 && CC != 1 && CC != 2 and CC == 0 && CC == 2 && CC != 3.
+
+; RUN: llc < %s -verify-machineinstrs -mtriple=s390x-linux-gnu -O2 | FileCheck
%s
+
+; Test CC == 0 && CC != 1.
+define signext range(i32 0, 43) i32 @foo_01(i32 noundef signext %x) {
+; CHECK-LABEL: foo_01:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: #APP
+; CHECK-NEXT: ahi %r2, 42
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: lghi %r2, 42
+; CHECK-NEXT: ber %r14
+; CHECK-NEXT: .LBB0_1: # %entry
+; CHECK-NEXT: lghi %r2, 0
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call { i32, i32 } asm "ahi $0,42\0A", "=d,={@cc},0"(i32 %x) #2
+ %asmresult1 = extractvalue { i32, i32 } %0, 1
+ %1 = icmp ult i32 %asmresult1, 4
+ tail call void @llvm.assume(i1 %1)
+ %cmp = icmp eq i32 %asmresult1, 0
+ %cond = select i1 %cmp, i32 42, i32 0
+ ret i32 %cond
+}
+
+declare void @llvm.assume(i1 noundef) #1
+
+; Test CC == 0 && CC != 2
+define signext range(i32 0, 43) i32 @foo_02(i32 noundef signext %x) {
+; CHECK-LABEL: foo_02:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: #APP
+; CHECK-NEXT: ahi %r2, 42
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: lghi %r2, 42
+; CHECK-NEXT: ber %r14
+; CHECK-NEXT: .LBB1_1: # %entry
+; CHECK-NEXT: lghi %r2, 0
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call { i32, i32 } asm "ahi $0,42\0A", "=d,={@cc},0"(i32 %x) #2
+ %asmresult1 = extractvalue { i32, i32 } %0, 1
+ %1 = icmp ult i32 %asmresult1, 4
+ tail call void @llvm.assume(i1 %1)
+ %cmp = icmp eq i32 %asmresult1, 0
+ %cond = select i1 %cmp, i32 42, i32 0
+ ret i32 %cond
+}
+
+; Test CC == 0 && CC != 3.
+define signext range(i32 0, 43) i32 @foo_03(i32 noundef signext %x) {
+; CHECK-LABEL: foo_03:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: #APP
+; CHECK-NEXT: ahi %r2, 42
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: lghi %r2, 42
+; CHECK-NEXT: ber %r14
+; CHECK-NEXT: .LBB2_1: # %entry
+; CHECK-NEXT: lghi %r2, 0
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call { i32, i32 } asm "ahi $0,42\0A", "=d,={@cc},0"(i32 %x) #2
+ %asmresult1 = extractvalue { i32, i32 } %0, 1
+ %1 = icmp ult i32 %asmresult1, 4
+ tail call void @llvm.assume(i1 %1)
+ %cmp = icmp eq i32 %asmresult1, 0
+ %cond = select i1 %cmp, i32 42, i32 0
+ ret i32 %cond
+}
+
+; Test CC == 1 && CC != 2
+define signext range(i32 0, 43) i32 @foo_12(i32 noundef signext %x) {
+; CHECK-LABEL: foo_12:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: #APP
+; CHECK-NEXT: ahi %r2, 42
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: lghi %r2, 42
+; CHECK-NEXT: blr %r14
+; CHECK-NEXT: .LBB3_1: # %entry
+; CHECK-NEXT: lghi %r2, 0
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call { i32, i32 } asm "ahi $0,42\0A", "=d,={@cc},0"(i32 %x) #2
+ %asmresult1 = extractvalue { i32, i32 } %0, 1
+ %1 = icmp ult i32 %asmresult1, 4
+ tail call void @llvm.assume(i1 %1)
+ %cmp = icmp eq i32 %asmresult1, 1
+ %cond = select i1 %cmp, i32 42, i32 0
+ ret i32 %cond
+}
+
+; Test CC == 1 && CC != 3
+define signext range(i32 0, 43) i32 @foo_13(i32 noundef signext %x) {
+; CHECK-LABEL: foo_13:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: #APP
+; CHECK-NEXT: ahi %r2, 42
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: lghi %r2, 42
+; CHECK-NEXT: blr %r14
+; CHECK-NEXT: .LBB4_1: # %entry
+; CHECK-NEXT: lghi %r2, 0
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call { i32, i32 } asm "ahi $0,42\0A", "=d,={@cc},0"(i32 %x) #2
+ %asmresult1 = extractvalue { i32, i32 } %0, 1
+ %1 = icmp ult i32 %asmresult1, 4
+ tail call void @llvm.assume(i1 %1)
+ %cmp = icmp eq i32 %asmresult1, 1
+ %cond = select i1 %cmp, i32 42, i32 0
+ ret i32 %cond
+}
+
+; Test CC == 2 && CC != 3.
+define signext range(i32 0, 43) i32 @foo_23(i32 noundef signext %x) {
+; CHECK-LABEL: foo_23:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: #APP
+; CHECK-NEXT: ahi %r2, 42
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: lghi %r2, 42
+; CHECK-NEXT: bhr %r14
+; CHECK-NEXT: .LBB5_1: # %entry
+; CHECK-NEXT: lghi %r2, 0
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call { i32, i32 } asm "ahi $0,42\0A", "=d,={@cc},0"(i32 %x) #2
+ %asmresult1 = extractvalue { i32, i32 } %0, 1
+ %1 = icmp ult i32 %asmresult1, 4
+ tail call void @llvm.assume(i1 %1)
+ %cmp = icmp eq i32 %asmresult1, 2
+ %cond = select i1 %cmp, i32 42, i32 0
+ ret i32 %cond
+}
+
+; Test CC == 0 && CC != 1 && CC != 2.
+define signext range(i32 0, 43) i32 @foo_012(i32 noundef signext %x) {
+; CHECK-LABEL: foo_012:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: #APP
+; CHECK-NEXT: ahi %r2, 42
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: lghi %r2, 42
+; CHECK-NEXT: ber %r14
+; CHECK-NEXT: .LBB6_1: # %entry
+; CHECK-NEXT: lghi %r2, 0
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call { i32, i32 } asm "ahi $0,42\0A", "=d,={@cc},0"(i32 %x) #2
+ %asmresult1 = extractvalue { i32, i32 } %0, 1
+ %1 = icmp ult i32 %asmresult1, 4
+ tail call void @llvm.assume(i1 %1)
+ %cmp = icmp eq i32 %asmresult1, 0
+ %spec.select = select i1 %cmp, i32 42, i32 0
+ ret i32 %spec.select
+}
+
+; Test CC == 0 && CC != 1 && CC != 3.
+define signext range(i32 0, 43) i32 @foo_013(i32 noundef signext %x) {
+; CHECK-LABEL: foo_013:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: #APP
+; CHECK-NEXT: ahi %r2, 42
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: lghi %r2, 42
+; CHECK-NEXT: ber %r14
+; CHECK-NEXT: .LBB7_1: # %entry
+; CHECK-NEXT: lghi %r2, 0
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call { i32, i32 } asm "ahi $0,42\0A", "=d,={@cc},0"(i32 %x) #2
+ %asmresult1 = extractvalue { i32, i32 } %0, 1
+ %1 = icmp ult i32 %asmresult1, 4
+ tail call void @llvm.assume(i1 %1)
+ %cmp = icmp eq i32 %asmresult1, 0
+ %spec.select = select i1 %cmp, i32 42, i32 0
+ ret i32 %spec.select
+}
+
+; Test CC == 0 && CC != 2 && CC != 3.
+define signext range(i32 0, 43) i32 @foo_023(i32 noundef signext %x) {
+; CHECK-LABEL: foo_023:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: #APP
+; CHECK-NEXT: ahi %r2, 42
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: lghi %r2, 42
+; CHECK-NEXT: ber %r14
+; CHECK-NEXT: .LBB8_1: # %entry
+; CHECK-NEXT: lghi %r2, 0
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call { i32, i32 } asm "ahi $0,42\0A", "=d,={@cc},0"(i32 %x) #2
+ %asmresult1 = extractvalue { i32, i32 } %0, 1
+ %1 = icmp ult i32 %asmresult1, 4
+ tail call void @llvm.assume(i1 %1)
+ %cmp = icmp eq i32 %asmresult1, 0
+ %spec.select = select i1 %cmp, i32 42, i32 0
+ ret i32 %spec.select
+}
+
+; Test CC == 1 && CC != 2 && CC != 3.
+define signext range(i32 0, 43) i32 @foo_123(i32 noundef signext %x) {
+; CHECK-LABEL: foo_123:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: #APP
+; CHECK-NEXT: ahi %r2, 42
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: lghi %r2, 42
+; CHECK-NEXT: blr %r14
+; CHECK-NEXT: .LBB9_1: # %entry
+; CHECK-NEXT: lghi %r2, 0
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call { i32, i32 } asm "ahi $0,42\0A", "=d,={@cc},0"(i32 %x) #2
+ %asmresult1 = extractvalue { i32, i32 } %0, 1
+ %1 = icmp ult i32 %asmresult1, 4
+ tail call void @llvm.assume(i1 %1)
+ %cmp = icmp eq i32 %asmresult1, 1
+ %spec.select = select i1 %cmp, i32 42, i32 0
+ ret i32 %spec.select
+}
+
+; Test CC == 0 && CC == 1 && CC != 2.
+define noundef signext i32 @foo1_012(i32 noundef signext %x) {
+; CHECK-LABEL: foo1_012:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lghi %r2, 0
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call { i32, i32 } asm "ahi $0,42\0A", "=d,={@cc},0"(i32 %x) #2
+ %asmresult1 = extractvalue { i32, i32 } %0, 1
+ %1 = icmp ult i32 %asmresult1, 4
+ tail call void @llvm.assume(i1 %1)
+ ret i32 0
+}
+
+; Test CC == 0 && CC == 1 && CC != 3.
+define noundef signext i32 @foo1_013(i32 noundef signext %x) {
+; CHECK-LABEL: foo1_013:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lghi %r2, 0
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call { i32, i32 } asm "ahi $0,42\0A", "=d,={@cc},0"(i32 %x) #2
+ %asmresult1 = extractvalue { i32, i32 } %0, 1
+ %1 = icmp ult i32 %asmresult1, 4
+ tail call void @llvm.assume(i1 %1)
+ ret i32 0
+}
+
+; Test CC == 0 && CC == 2 && CC != 3
+define noundef signext i32 @foo1_023(i32 noundef signext %x) {
+; CHECK-LABEL: foo1_023:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lghi %r2, 0
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call { i32, i32 } asm "ahi $0,42\0A", "=d,={@cc},0"(i32 %x) #2
+ %asmresult1 = extractvalue { i32, i32 } %0, 1
+ %1 = icmp ult i32 %asmresult1, 4
+ tail call void @llvm.assume(i1 %1)
+ ret i32 0
+}
+
+; Test CC == 1 && CC == 2 && CC != 3.
+define noundef signext i32 @foo1_123(i32 noundef signext %x) {
+; CHECK-LABEL: foo1_123:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lghi %r2, 0
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call { i32, i32 } asm "ahi $0,42\0A", "=d,={@cc},0"(i32 %x) #2
+ %asmresult1 = extractvalue { i32, i32 } %0, 1
+ %1 = icmp ult i32 %asmresult1, 4
+ tail call void @llvm.assume(i1 %1)
+ ret i32 0
+}
+
+@a = global i32 0, align 4
+
+; Test CC == 0 && CC != 1.
+define range(i64 5, 9) i64 @fu_01() {
+; CHECK-LABEL: fu_01:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lgrl %r1, a@GOT
+; CHECK-NEXT: #APP
+; CHECK-NEXT: alsi 0(%r1), -1
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: lghi %r2, 5
+; CHECK-NEXT: ber %r14
+; CHECK-NEXT: .LBB14_1: # %entry
+; CHECK-NEXT: lghi %r2, 8
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call i32 asm " alsi $1,-1\0A",
"={@cc},=*QS,*QS,~{memory}"(ptr nonnull elementtype(i32) @a, ptr nonnull
elementtype(i32) @a) #2
+ %1 = icmp ult i32 %0, 4
+ tail call void @llvm.assume(i1 %1)
+ %cmp.i.not = icmp eq i32 %0, 0
+ %. = select i1 %cmp.i.not, i64 5, i64 8
+ ret i64 %.
+}
+
+; Test CC == 0 || CC != 2.
+define range(i64 5, 9) i64 @fu_02() {
+; CHECK-LABEL: fu_02:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lgrl %r1, a@GOT
+; CHECK-NEXT: #APP
+; CHECK-NEXT: alsi 0(%r1), -1
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: lghi %r2, 5
+; CHECK-NEXT: ber %r14
+; CHECK-NEXT: .LBB15_1: # %entry
+; CHECK-NEXT: lghi %r2, 8
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call i32 asm " alsi $1,-1\0A",
"={@cc},=*QS,*QS,~{memory}"(ptr nonnull elementtype(i32) @a, ptr nonnull
elementtype(i32) @a) #2
+ %1 = icmp ult i32 %0, 4
+ tail call void @llvm.assume(i1 %1)
+ %cmp.i.not = icmp eq i32 %0, 0
+ %. = select i1 %cmp.i.not, i64 5, i64 8
+ ret i64 %.
+}
+
+; Test CC == 0 || CC != 3.
+define range(i64 5, 9) i64 @fu_03() {
+; CHECK-LABEL: fu_03:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lgrl %r1, a@GOT
+; CHECK-NEXT: #APP
+; CHECK-NEXT: alsi 0(%r1), -1
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: lghi %r2, 5
+; CHECK-NEXT: ber %r14
+; CHECK-NEXT: .LBB16_1: # %entry
+; CHECK-NEXT: lghi %r2, 8
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call i32 asm " alsi $1,-1\0A",
"={@cc},=*QS,*QS,~{memory}"(ptr nonnull elementtype(i32) @a, ptr nonnull
elementtype(i32) @a) #2
+ %1 = icmp ult i32 %0, 4
+ tail call void @llvm.assume(i1 %1)
+ %cmp.i.not = icmp eq i32 %0, 0
+ %. = select i1 %cmp.i.not, i64 5, i64 8
+ ret i64 %.
+}
+
+; Test CC == 1 || CC != 2.
+define range(i64 5, 9) i64 @fu_12() {
+; CHECK-LABEL: fu_12:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lgrl %r1, a@GOT
+; CHECK-NEXT: #APP
+; CHECK-NEXT: alsi 0(%r1), -1
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: lghi %r2, 5
+; CHECK-NEXT: blr %r14
+; CHECK-NEXT: .LBB17_1: # %entry
+; CHECK-NEXT: lghi %r2, 8
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call i32 asm " alsi $1,-1\0A",
"={@cc},=*QS,*QS,~{memory}"(ptr nonnull elementtype(i32) @a, ptr nonnull
elementtype(i32) @a) #2
+ %1 = icmp ult i32 %0, 4
+ tail call void @llvm.assume(i1 %1)
+ %cmp.i.not = icmp eq i32 %0, 1
+ %. = select i1 %cmp.i.not, i64 5, i64 8
+ ret i64 %.
+}
+
+; Test CC == 1 || CC != 3.
+define range(i64 5, 9) i64 @fu_13() {
+; CHECK-LABEL: fu_13:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lgrl %r1, a@GOT
+; CHECK-NEXT: #APP
+; CHECK-NEXT: alsi 0(%r1), -1
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: lghi %r2, 5
+; CHECK-NEXT: blr %r14
+; CHECK-NEXT: .LBB18_1: # %entry
+; CHECK-NEXT: lghi %r2, 8
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call i32 asm " alsi $1,-1\0A",
"={@cc},=*QS,*QS,~{memory}"(ptr nonnull elementtype(i32) @a, ptr nonnull
elementtype(i32) @a) #2
+ %1 = icmp ult i32 %0, 4
+ tail call void @llvm.assume(i1 %1)
+ %cmp.i.not = icmp eq i32 %0, 1
+ %. = select i1 %cmp.i.not, i64 5, i64 8
+ ret i64 %.
+}
+
+; Test CC == 2 || CC != 3.
+define range(i64 5, 9) i64 @fu_23() {
+; CHECK-LABEL: fu_23:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lgrl %r1, a@GOT
+; CHECK-NEXT: #APP
+; CHECK-NEXT: alsi 0(%r1), -1
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: lghi %r2, 5
+; CHECK-NEXT: bhr %r14
+; CHECK-NEXT: .LBB19_1: # %entry
+; CHECK-NEXT: lghi %r2, 8
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call i32 asm " alsi $1,-1\0A",
"={@cc},=*QS,*QS,~{memory}"(ptr nonnull elementtype(i32) @a, ptr nonnull
elementtype(i32) @a) #2
+ %1 = icmp ult i32 %0, 4
+ tail call void @llvm.assume(i1 %1)
+ %cmp.i.not = icmp eq i32 %0, 2
+ %. = select i1 %cmp.i.not, i64 5, i64 8
+ ret i64 %.
+}
+
+; Test CC == 0 || CC != 1 || CC != 2.
+define range(i64 5, 9) i64 @fu_012() {
+; CHECK-LABEL: fu_012:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lgrl %r1, a@GOT
+; CHECK-NEXT: #APP
+; CHECK-NEXT: alsi 0(%r1), -1
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: lghi %r2, 5
+; CHECK-NEXT: ber %r14
+; CHECK-NEXT: .LBB20_1: # %entry
+; CHECK-NEXT: lghi %r2, 8
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call i32 asm " alsi $1,-1\0A",
"={@cc},=*QS,*QS,~{memory}"(ptr nonnull elementtype(i32) @a, ptr nonnull
elementtype(i32) @a) #2
+ %1 = icmp ult i32 %0, 4
+ tail call void @llvm.assume(i1 %1)
+ %cmp.i.not = icmp eq i32 %0, 0
+ %. = select i1 %cmp.i.not, i64 5, i64 8
+ ret i64 %.
+}
+
+; Test CC == 0 || CC != 1 || CC != 3.
+define range(i64 5, 9) i64 @fu_013() {
+; CHECK-LABEL: fu_013:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lgrl %r1, a@GOT
+; CHECK-NEXT: #APP
+; CHECK-NEXT: alsi 0(%r1), -1
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: lghi %r2, 5
+; CHECK-NEXT: ber %r14
+; CHECK-NEXT: .LBB21_1: # %entry
+; CHECK-NEXT: lghi %r2, 8
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call i32 asm " alsi $1,-1\0A",
"={@cc},=*QS,*QS,~{memory}"(ptr nonnull elementtype(i32) @a, ptr nonnull
elementtype(i32) @a) #2
+ %1 = icmp ult i32 %0, 4
+ tail call void @llvm.assume(i1 %1)
+ %cmp.i.not = icmp eq i32 %0, 0
+ %. = select i1 %cmp.i.not, i64 5, i64 8
+ ret i64 %.
+}
+
+; Test CC == 0 || CC != 2 || CC != 3.
+define range(i64 5, 9) i64 @fu_023() {
+; CHECK-LABEL: fu_023:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lgrl %r1, a@GOT
+; CHECK-NEXT: #APP
+; CHECK-NEXT: alsi 0(%r1), -1
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: lghi %r2, 5
+; CHECK-NEXT: ber %r14
+; CHECK-NEXT: .LBB22_1: # %entry
+; CHECK-NEXT: lghi %r2, 8
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call i32 asm " alsi $1,-1\0A",
"={@cc},=*QS,*QS,~{memory}"(ptr nonnull elementtype(i32) @a, ptr nonnull
elementtype(i32) @a) #2
+ %1 = icmp ult i32 %0, 4
+ tail call void @llvm.assume(i1 %1)
+ %cmp.i.not = icmp eq i32 %0, 0
+ %. = select i1 %cmp.i.not, i64 5, i64 8
+ ret i64 %.
+}
+
+; Test CC == 1 || CC != 2 || CC != 3.
+define range(i64 5, 9) i64 @fu_123() {
+; CHECK-LABEL: fu_123:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lgrl %r1, a@GOT
+; CHECK-NEXT: #APP
+; CHECK-NEXT: alsi 0(%r1), -1
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: lghi %r2, 5
+; CHECK-NEXT: blr %r14
+; CHECK-NEXT: .LBB23_1: # %entry
+; CHECK-NEXT: lghi %r2, 8
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call i32 asm " alsi $1,-1\0A",
"={@cc},=*QS,*QS,~{memory}"(ptr nonnull elementtype(i32) @a, ptr nonnull
elementtype(i32) @a) #2
+ %1 = icmp ult i32 %0, 4
+ tail call void @llvm.assume(i1 %1)
+ %cmp.i.not = icmp eq i32 %0, 1
+ %. = select i1 %cmp.i.not, i64 5, i64 8
+ ret i64 %.
+}
+; Test CC == 0 && CC != 1.
+define void @bar_01() {
+; CHECK-LABEL: bar_01:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lgrl %r1, a@GOT
+; CHECK-NEXT: #APP
+; CHECK-NEXT: alsi 0(%r1), -1
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: jge dummy@PLT
+; CHECK-NEXT: .LBB24_1: # %if.end
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call i32 asm " alsi $1,-1\0A",
"={@cc},=*QS,*QS,~{memory}"(ptr nonnull elementtype(i32) @a, ptr nonnull
elementtype(i32) @a) #3
+ %1 = icmp ult i32 %0, 4
+ tail call void @llvm.assume(i1 %1)
+ %cmp.i.not = icmp eq i32 %0, 0
+ br i1 %cmp.i.not, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ tail call void @dummy() #3
+ br label %if.end
+
+if.end: ; preds = %if.then, %entry
+ ret void
+}
+
+; Tset CC == 0 || CC == 1 || CC != 2.
+define noundef i64 @fu1_012() {
+; CHECK-LABEL: fu1_012:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lgrl %r1, a@GOT
+; CHECK-NEXT: #APP
+; CHECK-NEXT: alsi 0(%r1), -1
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: lghi %r2, 8
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call i32 asm " alsi $1,-1\0A",
"={@cc},=*QS,*QS,~{memory}"(ptr nonnull elementtype(i32) @a, ptr nonnull
elementtype(i32) @a) #2
+ %1 = icmp ult i32 %0, 4
+ tail call void @llvm.assume(i1 %1)
+ ret i64 8
+}
+
+; Tset CC == 0 || CC == 1 || CC != 3.
+define noundef i64 @fu1_013() {
+; CHECK-LABEL: fu1_013:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lgrl %r1, a@GOT
+; CHECK-NEXT: #APP
+; CHECK-NEXT: alsi 0(%r1), -1
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: lghi %r2, 8
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call i32 asm " alsi $1,-1\0A",
"={@cc},=*QS,*QS,~{memory}"(ptr nonnull elementtype(i32) @a, ptr nonnull
elementtype(i32) @a) #2
+ %1 = icmp ult i32 %0, 4
+ tail call void @llvm.assume(i1 %1)
+ ret i64 8
+}
+
+; Tset CC == 0 || CC == 2 || CC != 3.
+define noundef i64 @fu1_023() {
+; CHECK-LABEL: fu1_023:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lgrl %r1, a@GOT
+; CHECK-NEXT: #APP
+; CHECK-NEXT: alsi 0(%r1), -1
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: lghi %r2, 8
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call i32 asm " alsi $1,-1\0A",
"={@cc},=*QS,*QS,~{memory}"(ptr nonnull elementtype(i32) @a, ptr nonnull
elementtype(i32) @a) #2
+ %1 = icmp ult i32 %0, 4
+ tail call void @llvm.assume(i1 %1)
+ ret i64 8
+}
+
+; Tset CC == 1 || CC == 2 || CC != 3.
+define noundef i64 @fu1_123() {
+; CHECK-LABEL: fu1_123:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lgrl %r1, a@GOT
+; CHECK-NEXT: #APP
+; CHECK-NEXT: alsi 0(%r1), -1
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: lghi %r2, 8
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call i32 asm " alsi $1,-1\0A",
"={@cc},=*QS,*QS,~{memory}"(ptr nonnull elementtype(i32) @a, ptr nonnull
elementtype(i32) @a) #2
+ %1 = icmp ult i32 %0, 4
+ tail call void @llvm.assume(i1 %1)
+ ret i64 8
+}
+
+declare void @dummy() local_unnamed_addr #1
+
+; Test CC == 0 && CC != 2
+define void @bar_02() {
+; CHECK-LABEL: bar_02:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lgrl %r1, a@GOT
+; CHECK-NEXT: #APP
+; CHECK-NEXT: alsi 0(%r1), -1
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: jge dummy@PLT
+; CHECK-NEXT: .LBB29_1: # %if.end
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call i32 asm " alsi $1,-1\0A",
"={@cc},=*QS,*QS,~{memory}"(ptr nonnull elementtype(i32) @a, ptr nonnull
elementtype(i32) @a) #3
+ %1 = icmp ult i32 %0, 4
+ tail call void @llvm.assume(i1 %1)
+ %cmp.i.not = icmp eq i32 %0, 0
+ br i1 %cmp.i.not, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ tail call void @dummy() #3
+ br label %if.end
+
+if.end: ; preds = %if.then, %entry
+ ret void
+}
+
+; Test CC == 0 && CC != 3.
+define void @bar_03() {
+; CHECK-LABEL: bar_03:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lgrl %r1, a@GOT
+; CHECK-NEXT: #APP
+; CHECK-NEXT: alsi 0(%r1), -1
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: jge dummy@PLT
+; CHECK-NEXT: .LBB30_1: # %if.end
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call i32 asm " alsi $1,-1\0A",
"={@cc},=*QS,*QS,~{memory}"(ptr nonnull elementtype(i32) @a, ptr nonnull
elementtype(i32) @a) #3
+ %1 = icmp ult i32 %0, 4
+ tail call void @llvm.assume(i1 %1)
+ %cmp.i.not = icmp eq i32 %0, 0
+ br i1 %cmp.i.not, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ tail call void @dummy() #3
+ br label %if.end
+
+if.end: ; preds = %if.then, %entry
+ ret void
+}
+
+; Test CC == 1 && CC != 2
+define void @bar_12() {
+; CHECK-LABEL: bar_12:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lgrl %r1, a@GOT
+; CHECK-NEXT: #APP
+; CHECK-NEXT: alsi 0(%r1), -1
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: jgl dummy@PLT
+; CHECK-NEXT: .LBB31_1: # %if.end
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call i32 asm " alsi $1,-1\0A",
"={@cc},=*QS,*QS,~{memory}"(ptr nonnull elementtype(i32) @a, ptr nonnull
elementtype(i32) @a) #3
+ %1 = icmp ult i32 %0, 4
+ tail call void @llvm.assume(i1 %1)
+ %cmp.i.not = icmp eq i32 %0, 1
+ br i1 %cmp.i.not, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ tail call void @dummy() #3
+ br label %if.end
+
+if.end: ; preds = %if.then, %entry
+ ret void
+}
+
+; Test CC == 1 && CC != 3.
+define void @bar_13() {
+; CHECK-LABEL: bar_13:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lgrl %r1, a@GOT
+; CHECK-NEXT: #APP
+; CHECK-NEXT: alsi 0(%r1), -1
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: jgl dummy@PLT
+; CHECK-NEXT: .LBB32_1: # %if.end
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call i32 asm " alsi $1,-1\0A",
"={@cc},=*QS,*QS,~{memory}"(ptr nonnull elementtype(i32) @a, ptr nonnull
elementtype(i32) @a) #3
+ %1 = icmp ult i32 %0, 4
+ tail call void @llvm.assume(i1 %1)
+ %cmp.i.not = icmp eq i32 %0, 1
+ br i1 %cmp.i.not, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ tail call void @dummy() #3
+ br label %if.end
+
+if.end: ; preds = %if.then, %entry
+ ret void
+}
+
+; Test CC == 2 && CC != 3.
+define void @bar_23() {
+; CHECK-LABEL: bar_23:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lgrl %r1, a@GOT
+; CHECK-NEXT: #APP
+; CHECK-NEXT: alsi 0(%r1), -1
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: jgh dummy@PLT
+; CHECK-NEXT: .LBB33_1: # %if.end
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call i32 asm " alsi $1,-1\0A",
"={@cc},=*QS,*QS,~{memory}"(ptr nonnull elementtype(i32) @a, ptr nonnull
elementtype(i32) @a) #3
+ %1 = icmp ult i32 %0, 4
+ tail call void @llvm.assume(i1 %1)
+ %cmp.i.not = icmp eq i32 %0, 2
+ br i1 %cmp.i.not, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ tail call void @dummy() #3
+ br label %if.end
+
+if.end: ; preds = %if.then, %entry
+ ret void
+}
+
+; Test CC == 0 && CC != 1 && CC != 3.
+define void @bar_012() {
+; CHECK-LABEL: bar_012:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lgrl %r1, a@GOT
+; CHECK-NEXT: #APP
+; CHECK-NEXT: alsi 0(%r1), -1
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: jge dummy@PLT
+; CHECK-NEXT: .LBB34_1: # %if.end
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call i32 asm " alsi $1,-1\0A",
"={@cc},=*QS,*QS,~{memory}"(ptr nonnull elementtype(i32) @a, ptr nonnull
elementtype(i32) @a) #3
+ %1 = icmp ult i32 %0, 4
+ tail call void @llvm.assume(i1 %1)
+ %cmp.i.not = icmp eq i32 %0, 0
+ br i1 %cmp.i.not, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ tail call void @dummy() #3
+ br label %if.end
+
+if.end: ; preds = %if.then, %entry
+ ret void
+}
+
+; Test CC == 0 && CC != 1 && CC != 3.
+define void @bar_013() {
+; CHECK-LABEL: bar_013:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lgrl %r1, a@GOT
+; CHECK-NEXT: #APP
+; CHECK-NEXT: alsi 0(%r1), -1
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: jge dummy@PLT
+; CHECK-NEXT: .LBB35_1: # %if.end
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call i32 asm " alsi $1,-1\0A",
"={@cc},=*QS,*QS,~{memory}"(ptr nonnull elementtype(i32) @a, ptr nonnull
elementtype(i32) @a) #3
+ %1 = icmp ult i32 %0, 4
+ tail call void @llvm.assume(i1 %1)
+ %cmp.i.not = icmp eq i32 %0, 0
+ br i1 %cmp.i.not, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ tail call void @dummy() #3
+ br label %if.end
+
+if.end: ; preds = %if.then, %entry
+ ret void
+}
+
+; Test CC == 0 && CC != 2 && CC != 3.
+define void @bar_023() {
+; CHECK-LABEL: bar_023:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lgrl %r1, a@GOT
+; CHECK-NEXT: #APP
+; CHECK-NEXT: alsi 0(%r1), -1
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: jge dummy@PLT
+; CHECK-NEXT: .LBB36_1: # %if.end
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call i32 asm " alsi $1,-1\0A",
"={@cc},=*QS,*QS,~{memory}"(ptr nonnull elementtype(i32) @a, ptr nonnull
elementtype(i32) @a) #3
+ %1 = icmp ult i32 %0, 4
+ tail call void @llvm.assume(i1 %1)
+ %cmp.i.not = icmp eq i32 %0, 0
+ br i1 %cmp.i.not, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ tail call void @dummy() #3
+ br label %if.end
+
+if.end: ; preds = %if.then, %entry
+ ret void
+}
+
+; Test CC == 1 && CC != 2 && CC != 3.
+define void @bar_123() {
+; CHECK-LABEL: bar_123:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lgrl %r1, a@GOT
+; CHECK-NEXT: #APP
+; CHECK-NEXT: alsi 0(%r1), -1
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: jgl dummy@PLT
+; CHECK-NEXT: .LBB37_1: # %if.end
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call i32 asm " alsi $1,-1\0A",
"={@cc},=*QS,*QS,~{memory}"(ptr nonnull elementtype(i32) @a, ptr nonnull
elementtype(i32) @a) #3
+ %1 = icmp ult i32 %0, 4
+ tail call void @llvm.assume(i1 %1)
+ %cmp.i.not = icmp eq i32 %0, 1
+ br i1 %cmp.i.not, label %if.then, label %if.end
+
+if.then: ; preds = %entry
+ tail call void @dummy() #3
+ br label %if.end
+
+if.end: ; preds = %if.then, %entry
+ ret void
+}
+
+; Test CC == 0 && CC == 1 && CC != 2.
+define void @bar1_012() {
+; CHECK-LABEL: bar1_012:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lgrl %r1, a@GOT
+; CHECK-NEXT: #APP
+; CHECK-NEXT: alsi 0(%r1), -1
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call i32 asm " alsi $1,-1\0A",
"={@cc},=*QS,*QS,~{memory}"(ptr nonnull elementtype(i32) @a, ptr nonnull
elementtype(i32) @a) #3
+ %1 = icmp ult i32 %0, 4
+ tail call void @llvm.assume(i1 %1)
+ ret void
+}
+
+; Test CC == 0 && CC == 1 && CC != 3.
+define void @bar1_013() {
+; CHECK-LABEL: bar1_013:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lgrl %r1, a@GOT
+; CHECK-NEXT: #APP
+; CHECK-NEXT: alsi 0(%r1), -1
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call i32 asm " alsi $1,-1\0A",
"={@cc},=*QS,*QS,~{memory}"(ptr nonnull elementtype(i32) @a, ptr nonnull
elementtype(i32) @a) #3
+ %1 = icmp ult i32 %0, 4
+ tail call void @llvm.assume(i1 %1)
+ ret void
+}
+
+; Test CC == 0 && CC == 2 && CC != 3.
+define void @bar1_023() {
+; CHECK-LABEL: bar1_023:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: lgrl %r1, a@GOT
+; CHECK-NEXT: #APP
+; CHECK-NEXT: alsi 0(%r1), -1
+; CHECK-EMPTY:
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: br %r14
+entry:
+ %0 = tail call i32 asm " alsi $1,-1\0A",
"={@cc},=*QS,*QS,~{memory}"(ptr nonnull elementtype(i32) @a, ptr nonnull
elementtype(i32) @a) #3
+ %1 = icmp ult i32 %0, 4
+ tail call void @llvm.assume(i1 %1)
+ ret void
+}
+
+; Test CC == 1 && CC == 2 && CC !=3.
----------------
uweigand wrote:
This of course is tautologically false ...
https://github.com/llvm/llvm-project/pull/125970
_______________________________________________
cfe-commits mailing list
[email protected]
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
