github-actions[bot] wrote:
<!--LLVM CODE FORMAT COMMENT: {clang-format}-->
:warning: C/C++ code formatter, clang-format found issues in your code.
:warning:
<details>
<summary>
You can test this locally with the following command:
</summary>
``````````bash
git-clang-format --diff origin/main HEAD --extensions cpp,c --
clang/test/CIR/CodeGenBuiltins/X86/avx2-builtins.c
clang/test/CIR/CodeGenBuiltins/X86/sse41-builtins.c
clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
clang/test/CIR/CodeGenBuiltins/X86/avx512f-builtins.c
clang/test/CIR/CodeGenBuiltins/X86/sse2-builtins.c --diff_from_common_commit
``````````
:warning:
The reproduction instructions above might return results for more than one PR
in a stack if you are using a stacked PR workflow. You can limit the results by
changing `origin/main` to the base branch/commit you want to compare against.
:warning:
</details>
<details>
<summary>
View the diff from clang-format here.
</summary>
``````````diff
diff --git a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
index 618ce75bc..21c14fb51 100644
--- a/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
+++ b/clang/lib/CIR/CodeGen/CIRGenBuiltinX86.cpp
@@ -114,46 +114,46 @@ static mlir::Value emitX86MaskLogic(CIRGenBuilderTy
&builder,
return builder.createBitcast(builder.createBinop(loc, lhs, binOpKind, rhs),
ops[0].getType());
-static mlir::Value emitX86Muldq(CIRGenFunction &cgf, const CallExpr *expr,
- bool isSigned,
- SmallVectorImpl<mlir::Value> &ops) {
- CIRGenBuilderTy &builder = cgf.getBuilder();
- mlir::Location loc = cgf.getLoc(expr->getExprLoc());
- mlir::Type ty = ops[0].getType();
- unsigned tyPrimitiveSizeInBits =
- cgf.cgm.getDataLayout().getTypeSizeInBits(ty);
- mlir::Value lhs, rhs;
- // in cir, if a shiftOperation is shift right,it will be translated into Ashr
- // or lShr automatically in match and rewrite stage according to its
operand's
- // type
- if (isSigned) {
- ty =
- cir::VectorType::get(builder.getSInt64Ty(), tyPrimitiveSizeInBits /
64);
- cir::ConstantOp shiftAmt =
- builder.getConstant(loc, cir::IntAttr::get(builder.getSInt64Ty(), 32));
- cir::VecSplatOp shiftSplatVecOp =
- cir::VecSplatOp::create(builder, loc, ty, shiftAmt.getResult());
- mlir::Value shiftSplatValue = shiftSplatVecOp.getResult();
- lhs = builder.createBitcast(loc, ops[0], ty);
- rhs = builder.createBitcast(loc, ops[1], ty);
- lhs = builder.createShift(loc, lhs, shiftSplatValue, true);
- lhs = builder.createShift(loc, lhs, shiftSplatValue, false);
- rhs = builder.createShift(loc, rhs, shiftSplatValue, true);
- rhs = builder.createShift(loc, rhs, shiftSplatValue, false);
- } else {
- ty =
- cir::VectorType::get(builder.getSInt64Ty(), tyPrimitiveSizeInBits /
64);
- cir::ConstantOp maskScalar = builder.getConstant(
- loc, cir::IntAttr::get(builder.getSInt64Ty(), 0xffffffff));
- cir::VecSplatOp mask =
- cir::VecSplatOp::create(builder, loc, ty, maskScalar.getResult());
- lhs = builder.createBitcast(loc, ops[0], ty);
- rhs = builder.createBitcast(loc, ops[1], ty);
- lhs = builder.createAnd(loc, lhs, mask);
- rhs = builder.createAnd(loc, rhs, mask);
+ static mlir::Value emitX86Muldq(CIRGenFunction & cgf, const CallExpr *expr,
+ bool isSigned,
+ SmallVectorImpl<mlir::Value> &ops) {
+ CIRGenBuilderTy &builder = cgf.getBuilder();
+ mlir::Location loc = cgf.getLoc(expr->getExprLoc());
+ mlir::Type ty = ops[0].getType();
+ unsigned tyPrimitiveSizeInBits =
+ cgf.cgm.getDataLayout().getTypeSizeInBits(ty);
+ mlir::Value lhs, rhs;
+ // in cir, if a shiftOperation is shift right,it will be translated into
+ // Ashr or lShr automatically in match and rewrite stage according to its
+ // operand's type
+ if (isSigned) {
+ ty = cir::VectorType::get(builder.getSInt64Ty(),
+ tyPrimitiveSizeInBits / 64);
+ cir::ConstantOp shiftAmt = builder.getConstant(
+ loc, cir::IntAttr::get(builder.getSInt64Ty(), 32));
+ cir::VecSplatOp shiftSplatVecOp =
+ cir::VecSplatOp::create(builder, loc, ty, shiftAmt.getResult());
+ mlir::Value shiftSplatValue = shiftSplatVecOp.getResult();
+ lhs = builder.createBitcast(loc, ops[0], ty);
+ rhs = builder.createBitcast(loc, ops[1], ty);
+ lhs = builder.createShift(loc, lhs, shiftSplatValue, true);
+ lhs = builder.createShift(loc, lhs, shiftSplatValue, false);
+ rhs = builder.createShift(loc, rhs, shiftSplatValue, true);
+ rhs = builder.createShift(loc, rhs, shiftSplatValue, false);
+ } else {
+ ty = cir::VectorType::get(builder.getSInt64Ty(),
+ tyPrimitiveSizeInBits / 64);
+ cir::ConstantOp maskScalar = builder.getConstant(
+ loc, cir::IntAttr::get(builder.getSInt64Ty(), 0xffffffff));
+ cir::VecSplatOp mask =
+ cir::VecSplatOp::create(builder, loc, ty, maskScalar.getResult());
+ lhs = builder.createBitcast(loc, ops[0], ty);
+ rhs = builder.createBitcast(loc, ops[1], ty);
+ lhs = builder.createAnd(loc, lhs, mask);
+ rhs = builder.createAnd(loc, rhs, mask);
+ }
+ return builder.createMul(loc, lhs, rhs);
}
- return builder.createMul(loc, lhs, rhs);
-}
mlir::Value CIRGenFunction::emitX86BuiltinExpr(unsigned builtinID,
const CallExpr *expr) {
``````````
</details>
https://github.com/llvm/llvm-project/pull/169853
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