Author: dsanders Date: Wed Feb 4 08:25:47 2015 New Revision: 228143 URL: http://llvm.org/viewvc/llvm-project?rev=228143&view=rev Log: Preserve early clobber flag when using named registers in inline assembly.
Summary: Named registers with the constraint "=&r" currently lose the early clobber flag and turn into "=r" when converted to LLVM-IR. This patch correctly passes it on. Reviewers: atanasyan Reviewed By: atanasyan Subscribers: cfe-commits Differential Revision: http://reviews.llvm.org/D7346 Modified: cfe/trunk/lib/CodeGen/CGStmt.cpp cfe/trunk/test/CodeGen/arm-asm-variable.c cfe/trunk/test/CodeGen/asm-reg-var-local.c Modified: cfe/trunk/lib/CodeGen/CGStmt.cpp URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/lib/CodeGen/CGStmt.cpp?rev=228143&r1=228142&r2=228143&view=diff ============================================================================== --- cfe/trunk/lib/CodeGen/CGStmt.cpp (original) +++ cfe/trunk/lib/CodeGen/CGStmt.cpp Wed Feb 4 08:25:47 2015 @@ -1696,7 +1696,7 @@ SimplifyConstraint(const char *Constrain static std::string AddVariableConstraints(const std::string &Constraint, const Expr &AsmExpr, const TargetInfo &Target, CodeGenModule &CGM, - const AsmStmt &Stmt) { + const AsmStmt &Stmt, const bool EarlyClobber) { const DeclRefExpr *AsmDeclRef = dyn_cast<DeclRefExpr>(&AsmExpr); if (!AsmDeclRef) return Constraint; @@ -1721,7 +1721,7 @@ AddVariableConstraints(const std::string } // Canonicalize the register here before returning it. Register = Target.getNormalizedGCCRegisterName(Register); - return "{" + Register.str() + "}"; + return (EarlyClobber ? "&{" : "{") + Register.str() + "}"; } llvm::Value* @@ -1854,7 +1854,8 @@ void CodeGenFunction::EmitAsmStmt(const OutExpr = OutExpr->IgnoreParenNoopCasts(getContext()); OutputConstraint = AddVariableConstraints(OutputConstraint, *OutExpr, - getTarget(), CGM, S); + getTarget(), CGM, S, + Info.earlyClobber()); LValue Dest = EmitLValue(OutExpr); if (!Constraints.empty()) @@ -1959,7 +1960,7 @@ void CodeGenFunction::EmitAsmStmt(const InputConstraint = AddVariableConstraints(InputConstraint, *InputExpr->IgnoreParenNoopCasts(getContext()), - getTarget(), CGM, S); + getTarget(), CGM, S, Info.earlyClobber()); llvm::Value *Arg = EmitAsmInput(Info, InputExpr, Constraints); Modified: cfe/trunk/test/CodeGen/arm-asm-variable.c URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/arm-asm-variable.c?rev=228143&r1=228142&r2=228143&view=diff ============================================================================== --- cfe/trunk/test/CodeGen/arm-asm-variable.c (original) +++ cfe/trunk/test/CodeGen/arm-asm-variable.c Wed Feb 4 08:25:47 2015 @@ -17,7 +17,7 @@ int64_t foo(int64_t v, volatile int64_t : [_rl] "=&r" (rl), [_rh] "=&r" (rh) \ : [_p] "p" (p) : "memory"); - // CHECK: call { i32, i32 } asm sideeffect "ldrexd$0, $1, [$2]", "={r1},={r2},r,~{memory}"(i64* + // CHECK: call { i32, i32 } asm sideeffect "ldrexd$0, $1, [$2]", "=&{r1},=&{r2},r,~{memory}"(i64* return r; } Modified: cfe/trunk/test/CodeGen/asm-reg-var-local.c URL: http://llvm.org/viewvc/llvm-project/cfe/trunk/test/CodeGen/asm-reg-var-local.c?rev=228143&r1=228142&r2=228143&view=diff ============================================================================== --- cfe/trunk/test/CodeGen/asm-reg-var-local.c (original) +++ cfe/trunk/test/CodeGen/asm-reg-var-local.c Wed Feb 4 08:25:47 2015 @@ -2,6 +2,7 @@ // Exercise various use cases for local asm "register variables". int foo() { +// CHECK-LABEL: define i32 @foo() // CHECK: [[A:%[a-zA-Z0-9]+]] = alloca i32 register int a asm("rsi")=5; @@ -12,6 +13,29 @@ int foo() { // CHECK: store i32 [[Z]], i32* [[A]] a = 42; +// CHECK: store i32 42, i32* [[A]] + + asm volatile("; %0 This asm uses rsi" : : "r"(a)); +// CHECK: [[TMP:%[a-zA-Z0-9]+]] = load i32* [[A]] +// CHECK: call void asm sideeffect "; $0 This asm uses rsi", "{rsi},~{dirflag},~{fpsr},~{flags}"(i32 [[TMP]]) + + return a; +// CHECK: [[TMP1:%[a-zA-Z0-9]+]] = load i32* [[A]] +// CHECK: ret i32 [[TMP1]] +} + +int earlyclobber() { +// CHECK-LABEL: define i32 @earlyclobber() +// CHECK: [[A:%[a-zA-Z0-9]+]] = alloca i32 + + register int a asm("rsi")=5; +// CHECK: store i32 5, i32* [[A]] + + asm volatile("; %0 This asm defines rsi" : "=&r"(a)); +// CHECK: [[Z:%[a-zA-Z0-9]+]] = call i32 asm sideeffect "; $0 This asm defines rsi", "=&{rsi},~{dirflag},~{fpsr},~{flags}"() +// CHECK: store i32 [[Z]], i32* [[A]] + + a = 42; // CHECK: store i32 42, i32* [[A]] asm volatile("; %0 This asm uses rsi" : : "r"(a)); _______________________________________________ cfe-commits mailing list [email protected] http://lists.cs.uiuc.edu/mailman/listinfo/cfe-commits
