I think that makes sense. We need to enable ISD::FMA for the smaller types when AVX512 is enabled. Probably need to add AVX512 in PerformFMACombine and isFMAFasterThanFMulAndFAdd as well.
On Tue, Jun 23, 2015 at 1:23 PM, Ahmed Bougacha <[email protected]> wrote: > In http://reviews.llvm.org/D10617#192429, @craig.topper wrote: > > > Are the 512-bit intrinsics in clang's headers qualified with F16C and FMA > > defines? They don't seem to be in gcc's headers. And gcc doesn't seem to > > auto enable FMA or F16C when avx512 is specified. > > > > Similar question for the instructions in llvm. > > > They're not? > > But, if that's what you're getting at: if the defines have a 1-to-1 > mapping with the intrinsics/headers (I think they do?), then on second > thought, this isn't the right fix: +avx512f says nothing about whether we > support FMA/F16C intrinsics, only the AVX512F ones. > > Then the actual issue here is that, for fma and f16c, LLVM codegen relies > on +fma/+f16c only to mark say f32 ISD::FMA as legal, and generate > X86ISD::FMADD. Both of which are necessary to generate even the AVX512F > instruction, and this makes it impossible with +avx512f alone. > Does that make sense? If so I'll post a patch! > > -Ahmed > > > http://reviews.llvm.org/D10617 > > EMAIL PREFERENCES > http://reviews.llvm.org/settings/panel/emailpreferences/ > > > -- ~Craig
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