On Sep 20, 2010, at 6:08 PM, Eric Christopher wrote: > On Sep 20, 2010, at 6:07 PM, Chris Lattner wrote: > >> On Sep 20, 2010, at 6:02 PM, Eric Christopher wrote: >> >>>> @@ -37,6 +38,7 @@ >>>> BUILTIN(__builtin_ia32_psubb, "V8cV8cV8c", "") >>>> BUILTIN(__builtin_ia32_psubw, "V4sV4sV4s", "") >>>> BUILTIN(__builtin_ia32_psubd, "V2iV2iV2i", "") >>>> +BUILTIN(__builtin_ia32_psubq, "V1LLiV1LLiV1LLi", "") >>>> BUILTIN(__builtin_ia32_psubsb, "V8cV8cV8c", "") >>>> BUILTIN(__builtin_ia32_psubsw, "V4sV4sV4s", "") >>>> BUILTIN(__builtin_ia32_psubusb, "V8cV8cV8c", "") >>> >>> These were missing largely because the functionality works with '-' or '+' >>> on the >>> representative types and we'd not been adding them in cases where they were >>> missing since the intel intrinsics are the ones that we want people using. >>> >>> That said it looks like we've got a lot of them already. >> >> We're intentionally violating that model with MMX: we don't want generic >> vectors mapping onto mmx anymore. > > Figured it was something like that. Might be good to separate them out in > the file with a comment. > I segregated all of the MMX builtins into their own little group in the BuiltinsX86.def file. I can expand the comment to explain what we're doing with the MMX builtins.
I added these here for completeness (they're in the llvm/IntrinsicsX86.td file). As Chris mentioned, all of the MMX vector types are going to be bitcast to x86_mmx, fed into the MMX intrinsic, and the result bitcast to the builtin's return type. Any LLVM-native instructions will expand those types (<1 x i64>, <2 x i32>, etc.) into larger vector types and use SSE (or whatever) for them. It may be possible to optimize this for + and - (i.e., automagically generate an MMX instruction for the '+' in "_mm_add_pi16(a, b) + _mm_add_pi16(c, d)"), but that would take caring about MMX performance. :-) -bw _______________________________________________ cfe-commits mailing list [email protected] http://lists.cs.uiuc.edu/mailman/listinfo/cfe-commits
