Author: hhinnant
Date: Tue Oct 5 12:22:28 2010
New Revision: 115633
URL: http://llvm.org/viewvc/llvm-project?rev=115633&view=rev
Log:
A compiler writer's guide to <atomic>, minor update
Modified:
libcxx/trunk/www/atomic_design.html
Modified: libcxx/trunk/www/atomic_design.html
URL:
http://llvm.org/viewvc/llvm-project/libcxx/trunk/www/atomic_design.html?rev=115633&r1=115632&r2=115633&view=diff
==============================================================================
--- libcxx/trunk/www/atomic_design.html (original)
+++ libcxx/trunk/www/atomic_design.html Tue Oct 5 12:22:28 2010
@@ -377,11 +377,17 @@
<p>
On some platforms, the compiler vendor can offer some or even all of the above
intrinsics at one or more weaker levels of memory synchronization. This might
-lead for example to not issuing an <tt>mfense</tt> instruction on the x86. If
-the compiler does not offer any given operation, at any given memory ordering
+lead for example to not issuing an <tt>mfense</tt> instruction on the x86.
+</p>
+
+<p>
+If the compiler does not offer any given operation, at any given memory
ordering
level, the library will automatically attempt to call the next highest memory
ordering operation. This continues up to <tt>seq_cst</tt>, and if that doesn't
-exist, then the library takes over and does the job with a <tt>mutex</tt>.
+exist, then the library takes over and does the job with a <tt>mutex</tt>.
This
+is a compile-time search & selection operation. At run time, the
+application will only see the few inlined assembly instructions for the
selected
+intrinsic.
</p>
<p>
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