Fixed in r178598 after updating the compile error. Thanks! ~Aaron
On Fri, Mar 29, 2013 at 12:17 PM, Benjamin Kramer <[email protected]> wrote: > > On 16.03.2013, at 16:21, Aaron Ballman <[email protected]> wrote: > >> I did some more digging and found out that Ivy Bridge has the same >> behavior as Sandy Bridge - the Pentium models don't have AVX support >> (they seem to be more similar to the corei7). So I've revised the >> patch to include Ivy Bridge, and fixed OSHasAVXSupport to return false >> if we don't know how to handle the inline assembly for it. >> >> Btw, as for the < Windows 7 SP1 issues -- that's why we're checking > >> for OS support using the xgetbv instruction.Index: lib/Support/Host.cpp >> =================================================================== >> --- lib/Support/Host.cpp (revision 177222) >> +++ lib/Support/Host.cpp (working copy) >> @@ -112,6 +112,18 @@ >> #endif >> } >> >> +static bool OSHasAVXSupport() { >> +#if defined(__GNUC__) >> + int rEAX, rEDX; >> + __asm__ ("xgetbv" : "=a" (rEAX), "=d" (rEDX) : "c" (0)); >> +#elif defined(_MSC_VER) >> + unsigned long long rEAX = _xgetbv(_XCR_XFEATURE_ENABLED_MASK); >> +#else >> + return false; >> +#endif >> + return (rEAX & 6) == 6; > > I don't think this compiles when neither __GNUC__ nor _MSC_VER is set. > > Otherwise LGTM. We probably want the same for AVX-supporting AMD CPUs, but > this patch is a good first step. > > - Ben > >> +} >> + >> static void DetectX86FamilyModel(unsigned EAX, unsigned &Family, >> unsigned &Model) { >> Family = (EAX >> 8) & 0xf; // Bits 8 - 11 >> @@ -134,6 +146,10 @@ >> DetectX86FamilyModel(EAX, Family, Model); >> >> bool HasSSE3 = (ECX & 0x1); >> + // If CPUID indicates support for XSAVE, XRESTORE and AVX, and XGETBV >> + // indicates that the AVX registers will be saved and restored on context >> + // switch, when we have full AVX support. >> + bool HasAVX = (ECX & ((1 << 28) | (1 << 27))) != 0 && OSHasAVXSupport(); >> GetX86CpuIDAndInfo(0x80000001, &EAX, &EBX, &ECX, &EDX); >> bool Em64T = (EDX >> 29) & 0x1; >> >> @@ -243,11 +259,15 @@ >> case 42: // Intel Core i7 processor. All processors are manufactured >> // using the 32 nm process. >> case 45: >> - return "corei7-avx"; >> + // Not all Sandy Bridge processors support AVX (such as the Pentium >> + // versions instead of the i7 versions). >> + return HasAVX ? "corei7-avx" : "corei7"; >> >> // Ivy Bridge: >> case 58: >> - return "core-avx-i"; >> + // Not all Ivy Bridge processors support AVX (such as the Pentium >> + // versions instead of the i7 versions). >> + return HasAVX ? "core-avx-i" : "corei7"; >> >> case 28: // Most 45 nm Intel Atom processors >> case 38: // 45 nm Atom Lincroft _______________________________________________ cfe-commits mailing list [email protected] http://lists.cs.uiuc.edu/mailman/listinfo/cfe-commits
