Hi Kevin,
Just one minor issue in test/CodeGen/AArch64/neon-copy.ll:
define <8 x i8> @test_vcopy_lane_s8(<8 x i8> %v1, <8 x i8> %v2) {
;CHECK: ins v0.b[5], v1.b[3]
%vset_lane = shufflevector <8 x i8> %v1, <8 x i8> %v2, <8 x i32> <i32 0, i32
1, i32 2, i32 3, i32 4, i32 11, i32 6, i32 7>
ret <8 x i8> %vset_lane
}
The CHECK registers are fixed to v0 and v1. If the register allocating order is
changed, the test may be failed.
I just find other tests are using {{v[0-9]+}} instead.
Thanks,
-Hao
-----Original Message-----
From: [email protected] [mailto:[email protected]]
On Behalf Of Kevin Qin
Sent: Tuesday, October 08, 2013 6:33 AM
To: [email protected]; [email protected]
Cc: [email protected]; [email protected]
Subject: [PATCH] Implement aarch64 neon instruction class SIMD copy - LLVM
This patch implemented aarch64 neon SIMD copy instruction class.
I rebased this patch on latest truck.
This patch contains:
1. Implemented SIMD dup instruction.
2. Remove DupImm, use VDUP instead.
Known problem:
1. In AAPCS64, half float can serve as setters and getters for function, so
some ACLE intrinsic would receive or provide a variable with half float. But
this feature isn't supported by Clang at moment. Even when I hack diagnose
detector to avoid throwing error message, all half float will be converted to
i16 in IR.
2. There is no v4f16 in IR, which is used by some ACLE intrinsic.
Considering above problem, all ACLE intrinsic with half float isn't implemented
in these patches. We will try to figure out how to implement this feature.
Please review, thanks.
http://llvm-reviews.chandlerc.com/D1854
Files:
lib/Target/AArch64/AArch64ISelLowering.cpp
lib/Target/AArch64/AArch64ISelLowering.h
lib/Target/AArch64/AArch64InstrNEON.td
lib/Target/AArch64/AArch64RegisterInfo.td
test/CodeGen/AArch64/neon-copy.ll
test/MC/AArch64/neon-diagnostics.s
test/MC/AArch64/neon-simd-copy.s
_______________________________________________
cfe-commits mailing list
[email protected]
http://lists.cs.uiuc.edu/mailman/listinfo/cfe-commits
