Hi Ana, > But to force vmul_n_f64, vmul_lane_f64, vmul_laneq_f64 legacy intrinsics to > map to Neon scalar operations I had to add an aarch64 IR intrinsic.
I don't see why that's an issue in this case. Since floating-point operations take place in FP-registers anyway, there should be no pair with duplicated functionality. Could you give an example of some code that wouldn't work as expected with a natural IR mapping? Cheers. Tim. _______________________________________________ cfe-commits mailing list [email protected] http://lists.cs.uiuc.edu/mailman/listinfo/cfe-commits
