Hi,
Attached is the patch of adding predicate for AArch64 crypto instructions.
--
Thanks,
-Jiangning
diff --git a/include/clang/Basic/arm_neon.td b/include/clang/Basic/arm_neon.td
old mode 100644
new mode 100755
index e2e3d29..076a81f
--- a/include/clang/Basic/arm_neon.td
+++ b/include/clang/Basic/arm_neon.td
@@ -129,6 +129,7 @@ class Inst <string n, string p, string t, Op o> {
bit isScalarShift = 0;
bit isVCVT_N = 0;
bit isA64 = 0;
+ bit isCrypto = 0;
// Certain intrinsics have different names than their representative
// instructions. This field allows us to handle this correctly when we
@@ -893,6 +894,7 @@ def VEXT_A64 : WInst<"vext", "dddi",
////////////////////////////////////////////////////////////////////////////////
// Crypto
+let isCrypto = 1 in {
def AESE : SInst<"vaese", "ddd", "QUc">;
def AESD : SInst<"vaesd", "ddd", "QUc">;
def AESMC : SInst<"vaesmc", "dd", "QUc">;
@@ -909,6 +911,7 @@ def SHA1SU0 : SInst<"vsha1su0", "dddd", "QUi">;
def SHA256H : SInst<"vsha256h", "dddd", "QUi">;
def SHA256H2 : SInst<"vsha256h2", "dddd", "QUi">;
def SHA256SU1 : SInst<"vsha256su1", "dddd", "QUi">;
+}
////////////////////////////////////////////////////////////////////////////////
// Permutation
diff --git a/test/CodeGen/aarch64-neon-crypto.c b/test/CodeGen/aarch64-neon-crypto.c
index 968ef2e..240f379 100644
--- a/test/CodeGen/aarch64-neon-crypto.c
+++ b/test/CodeGen/aarch64-neon-crypto.c
@@ -1,6 +1,8 @@
// REQUIRES: aarch64-registered-target
// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon \
-// RUN: -ffp-contract=fast -S -O3 -o - %s | FileCheck %s
+// RUN: -target-feature +crypto -S -O3 -o - %s | FileCheck %s
+// RUN: not %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +neon \
+// RUN: -S -O3 -o - %s 2>&1 | FileCheck --check-prefix=CHECK-NO-CRYPTO %s
// Test new aarch64 intrinsics and types
@@ -8,6 +10,7 @@
uint8x16_t test_vaeseq_u8(uint8x16_t data, uint8x16_t key) {
// CHECK: test_vaeseq_u8
+ // CHECK-NO-CRYPTO: warning: implicit declaration of function 'vaeseq_u8' is invalid in C99
return vaeseq_u8(data, key);
// CHECK: aese {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
}
diff --git a/utils/TableGen/NeonEmitter.cpp b/utils/TableGen/NeonEmitter.cpp
old mode 100644
new mode 100755
index 5615666..b06b4e4
--- a/utils/TableGen/NeonEmitter.cpp
+++ b/utils/TableGen/NeonEmitter.cpp
@@ -2546,8 +2546,28 @@ void NeonEmitter::run(raw_ostream &OS) {
if (!isA64)
continue;
+ // Skip crypto temporarily, and will emit them all together at the end.
+ bool isCrypto = R->getValueAsBit("isCrypto");
+ if (isCrypto)
+ continue;
+
+ emitIntrinsic(OS, R, EmittedMap);
+ }
+
+ OS << "#ifdef __ARM_FEATURE_CRYPTO\n";
+
+ for (unsigned i = 0, e = RV.size(); i != e; ++i) {
+ Record *R = RV[i];
+
+ // Skip crypto temporarily, and will emit them all together at the end.
+ bool isCrypto = R->getValueAsBit("isCrypto");
+ if (!isCrypto)
+ continue;
+
emitIntrinsic(OS, R, EmittedMap);
}
+
+ OS << "#endif\n\n";
OS << "#endif\n\n";
diff --git a/lib/Target/AArch64/AArch64InstrNEON.td b/lib/Target/AArch64/AArch64InstrNEON.td
index 09d2876..1bdce72 100644
--- a/lib/Target/AArch64/AArch64InstrNEON.td
+++ b/lib/Target/AArch64/AArch64InstrNEON.td
@@ -7577,6 +7577,7 @@ class NeonI_Cryptoaes_2v<bits<2> size, bits<5> opcode,
(v16i8 VPR128:$Rn))))],
NoItinerary>{
let Constraints = "$src = $Rd";
+ let Predicates = [HasNEON, HasCrypto];
}
def AESE : NeonI_Cryptoaes_2v<0b00, 0b00100, "aese", int_arm_neon_aese>;
@@ -7604,6 +7605,7 @@ class NeonI_Cryptosha_vv<bits<2> size, bits<5> opcode,
(v4i32 VPR128:$Rn))))],
NoItinerary> {
let Constraints = "$src = $Rd";
+ let Predicates = [HasNEON, HasCrypto];
}
def SHA1SU1 : NeonI_Cryptosha_vv<0b00, 0b00001, "sha1su1",
@@ -7618,7 +7620,9 @@ class NeonI_Cryptosha_ss<bits<2> size, bits<5> opcode,
asmop # "\t$Rd, $Rn",
[(set (v1i32 FPR32:$Rd),
(v1i32 (opnode (v1i32 FPR32:$Rn))))],
- NoItinerary>;
+ NoItinerary> {
+ let Predicates = [HasNEON, HasCrypto];
+}
def SHA1H : NeonI_Cryptosha_ss<0b00, 0b00000, "sha1h", int_arm_neon_sha1h>;
@@ -7634,6 +7638,7 @@ class NeonI_Cryptosha3_vvv<bits<2> size, bits<3> opcode, string asmop,
(v4i32 VPR128:$Rm))))],
NoItinerary> {
let Constraints = "$src = $Rd";
+ let Predicates = [HasNEON, HasCrypto];
}
def SHA1SU0 : NeonI_Cryptosha3_vvv<0b00, 0b011, "sha1su0",
@@ -7653,6 +7658,7 @@ class NeonI_Cryptosha3_qqv<bits<2> size, bits<3> opcode, string asmop,
(v4i32 VPR128:$Rm))))],
NoItinerary> {
let Constraints = "$src = $Rd";
+ let Predicates = [HasNEON, HasCrypto];
}
def SHA256H : NeonI_Cryptosha3_qqv<0b00, 0b100, "sha256h",
@@ -7672,6 +7678,7 @@ class NeonI_Cryptosha3_qsv<bits<2> size, bits<3> opcode, string asmop,
(v4i32 VPR128:$Rm))))],
NoItinerary> {
let Constraints = "$src = $Rd";
+ let Predicates = [HasNEON, HasCrypto];
}
def SHA1C : NeonI_Cryptosha3_qsv<0b00, 0b000, "sha1c", int_aarch64_neon_sha1c>;
diff --git a/test/CodeGen/AArch64/neon-crypto.ll b/test/CodeGen/AArch64/neon-crypto.ll
index e4ae227..0283e0e 100644
--- a/test/CodeGen/AArch64/neon-crypto.ll
+++ b/test/CodeGen/AArch64/neon-crypto.ll
@@ -1,4 +1,5 @@
-; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon | FileCheck %s
+; RUN: llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon -mattr=+crypto | FileCheck %s
+; RUN: not llc < %s -verify-machineinstrs -mtriple=aarch64-none-linux-gnu -mattr=+neon 2>&1 | FileCheck --check-prefix=CHECK-NO-CRYPTO %s
declare <4 x i32> @llvm.arm.neon.sha256su1.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) #1
@@ -31,6 +32,7 @@ declare <16 x i8> @llvm.arm.neon.aese.v16i8(<16 x i8>, <16 x i8>) #1
define <16 x i8> @test_vaeseq_u8(<16 x i8> %data, <16 x i8> %key) {
; CHECK: test_vaeseq_u8:
; CHECK: aese {{v[0-9]+}}.16b, {{v[0-9]+}}.16b
+; CHECK-NO-CRYPTO: Cannot select: intrinsic %llvm.arm.neon.aese
entry:
%aese.i = tail call <16 x i8> @llvm.arm.neon.aese.v16i8(<16 x i8> %data, <16 x i8> %key)
ret <16 x i8> %aese.i
diff --git a/test/MC/AArch64/neon-crypto.s b/test/MC/AArch64/neon-crypto.s
index df6eee8..2952dd5 100644
--- a/test/MC/AArch64/neon-crypto.s
+++ b/test/MC/AArch64/neon-crypto.s
@@ -1,4 +1,5 @@
-// RUN: llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s | FileCheck %s
+// RUN: llvm-mc -triple=aarch64 -mattr=+neon -mattr=+crypto -show-encoding < %s | FileCheck %s
+// RUN: not llvm-mc -triple=aarch64 -mattr=+neon -show-encoding < %s 2>&1 | FileCheck -check-prefix=CHECK-NO-CRYPTO %s
// Check that the assembler can handle the documented syntax for AArch64
@@ -11,6 +12,7 @@
aesmc v0.16b, v1.16b
aesimc v0.16b, v1.16b
+// CHECK-NO-CRYPTO: error: instruction requires a CPU feature not currently enabled
// CHECK: aese v0.16b, v1.16b // encoding: [0x20,0x48,0x28,0x4e]
// CHECK: aesd v0.16b, v1.16b // encoding: [0x20,0x58,0x28,0x4e]
// CHECK: aesmc v0.16b, v1.16b // encoding: [0x20,0x68,0x28,0x4e]
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