[PATCH] headers: be a bit more careful about inline asm

[Saleem Abdulrasool]

Hi rnk,

The Intrin.h header unconditionally includes ia32intrin.h.  It also
unconditionally defines inline assembly routines.  The assembly used here is x86
specific.  Be more careful about only providing definitions if we are targeting
x86.  This is now more relevant as clang can target Windows on ARM where these
declarations may be included into user code.

http://reviews.llvm.org/D3558

Files:
  lib/Headers/Intrin.h
  lib/Headers/ia32intrin.h

Index: lib/Headers/Intrin.h
===================================================================
--- lib/Headers/Intrin.h
+++ lib/Headers/Intrin.h
@@ -575,6 +575,8 @@
   *a = *a | (1 << b);
   return x;
 }
+
+#if defined(__i386__) || defined(__x86_64__)
 static __inline__ unsigned char __attribute__((__always_inline__, __nodebug__))
 _interlockedbittestandset(long volatile *__BitBase, long __BitPos) {
   unsigned char __Res;
@@ -585,6 +587,8 @@
            : "Ir"(__BitPos));
   return __Res;
 }
+#endif
+
 #ifdef __x86_64__
 static __inline__ unsigned char __attribute__((__always_inline__, __nodebug__))
 _BitScanForward64(unsigned long *_Index, unsigned __int64 _Mask) {
@@ -836,6 +840,8 @@
 /*----------------------------------------------------------------------------*\
 |* Barriers
 \*----------------------------------------------------------------------------*/
+
+#if defined(__i386__) || defined(__x86_64__)
 static __inline__ void __attribute__((__always_inline__, __nodebug__))
 __attribute__((deprecated("use other intrinsics or C++11 atomics instead")))
 _ReadWriteBarrier(void) {
@@ -851,12 +857,15 @@
 _WriteBarrier(void) {
   __asm__ volatile ("" : : : "memory");
 }
+#endif
+
 #ifdef __x86_64__
 static __inline__ void __attribute__((__always_inline__, __nodebug__))
 __faststorefence(void) {
   __asm__ volatile("lock orq $0, (%%rsp)" : : : "memory");
 }
 #endif
+
 /*----------------------------------------------------------------------------*\
 |* readfs, readgs
 |* (Pointers in address space #256 and #257 are relative to the GS and FS
@@ -906,6 +915,8 @@
 /*----------------------------------------------------------------------------*\
 |* movs, stos
 \*----------------------------------------------------------------------------*/
+
+#if defined(__i386__) || defined(__x86_64__)
 static __inline__ void __attribute__((__always_inline__, __nodebug__))
 __movsb(unsigned char *__dst, unsigned char const *__src, size_t __n) {
   __asm__("rep movsb" : : "D"(__dst), "S"(__src), "c"(__n)
@@ -936,6 +947,8 @@
   __asm__("rep stosh" : : "D"(__dst), "a"(__x), "c"(__n)
                         : "%edi", "%ecx");
 }
+#endif
+
 #ifdef __x86_64__
 static __inline__ void __attribute__((__always_inline__, __nodebug__))
 __movsq(unsigned long long *__dst, unsigned long long const *__src, size_t __n) {
@@ -960,6 +973,8 @@
 _ReturnAddress(void) {
   return __builtin_return_address(0);
 }
+
+#if defined(__i386__) || defined(__x86_64__)
 static __inline__ void __attribute__((__always_inline__, __nodebug__))
 __cpuid(int __info[4], int __level) {
   __asm__ ("cpuid" : "=a"(__info[0]), "=b" (__info[1]), "=c"(__info[2]), "=d"(__info[3])
@@ -970,20 +985,24 @@
   __asm__ ("cpuid" : "=a"(__info[0]), "=b" (__info[1]), "=c"(__info[2]), "=d"(__info[3])
                    : "a"(__level), "c"(__ecx));
 }
+
 static __inline__ unsigned __int64 __cdecl __attribute__((__always_inline__, __nodebug__))
 _xgetbv(unsigned int __xcr_no) {
   unsigned int __eax, __edx;
   __asm__ ("xgetbv" : "=a" (__eax), "=d" (__edx) : "c" (__xcr_no));
   return ((unsigned __int64)__edx << 32) | __eax;
 }
+
 static __inline__ void __attribute__((__always_inline__, __nodebug__))
 __halt(void) {
   __asm__ volatile ("hlt");
 }
+#endif
 
 /*----------------------------------------------------------------------------*\
 |* Privileged intrinsics
 \*----------------------------------------------------------------------------*/
+#if defined(__i386__) || defined(__x86_64__)
 static __inline__ unsigned __int64 __attribute__((__always_inline__, __nodebug__))
 __readmsr(unsigned long __register) {
   // Loads the contents of a 64-bit model specific register (MSR) specified in
@@ -1009,6 +1028,7 @@
 __writecr3(unsigned int __cr3_val) {
   __asm__ ("mov %0, %%cr3" : : "q"(__cr3_val) : "memory");
 }
+#endif
 
 #ifdef __cplusplus
 }
Index: lib/Headers/ia32intrin.h
===================================================================
--- lib/Headers/ia32intrin.h
+++ lib/Headers/ia32intrin.h
@@ -52,8 +52,9 @@
                         :"flags"
                        );
 }
+#endif /* __x86_64__ */
 
-#else /* !__x86_64__ */
+#if defined(__i386__)
 static __inline__ unsigned int __attribute__((__always_inline__, __nodebug__))
 __readeflags(void)
 {
@@ -77,8 +78,9 @@
                         :"flags"
                        );
 }
-#endif /* !__x86_64__ */
+#endif /* __i386__ */
 
+#if defined(__i386__) || defined(__x86_64__)
 /* __rdtsc */
 static __inline__ unsigned long long __attribute__((__always_inline__, __nodebug__))
 __rdtsc(void) {
@@ -92,5 +94,6 @@
 }
 
 #define _rdtsc() __rdtsc()
+#endif
 
 #endif /* __IA32INTRIN_H */

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