================
Comment at: lib/Headers/Intrin.h:783
@@ +782,3 @@
+__faststorefence(void) {
+ __asm__ volatile ("lock orq $0,(%rsp)");
+}
----------------
David Ziman wrote:
> David Ziman wrote:
> > Reid Kleckner wrote:
> > > I think this needs to have a memory constraint to avoid reordering
> > > non-volatile loads and stores across it.
> > This instruction reads a memory address, or's it with the constant 0, and
> > writes it back to the same location with the lock prefix. That's
> > read-modify-write with lock prefix, and I believe the AMD and Intel manuals
> > state that this should be enough. I can provide references if you like.
> > It's also the same instruction emitted by MSVC.
> Alternatively, we could use sfence here. Are you a also looking to prevent
> the compiler from re-ordering this instruction? Will it do that?
I meant it needs to have a gcc inline asm style "memory" constraint, like so:
__asm__ volatile("lock orq $0, (%%rsp)" : : : "memory");
GCC doesn't parse inline assembly, so it needs the user to carefully spell out
the constraints on scheduling. Clang follows that model for gcc-style inline
asm.
http://reviews.llvm.org/D2600
_______________________________________________
cfe-commits mailing list
[email protected]
http://lists.cs.uiuc.edu/mailman/listinfo/cfe-commits
