rovka added a comment. Just some drive-by suggestions :)
================ Comment at: lib/Target/AArch64/AArch64ISelLowering.cpp:5747 + +PredicateConstraint isPredicateConstraint(StringRef Constraint) { + PredicateConstraint P = PredicateConstraint::Invalid; ---------------- Nit: I think get- or parsePredicateConstraint reads better, since this doesn't return a simple yes/no answer. ================ Comment at: test/CodeGen/AArch64/aarch64-sve-asm.ll:50 +; CHECK: [[ARG3:%[0-9]+]]:ppr = COPY $p0 +; CHECK: [[ARG4:%[0-9]+]]:ppr_3b = COPY [[ARG3]] +define <vscale x 8 x half> @test_svfadd_f16(<vscale x 16 x i1> %Pg, <vscale x 8 x half> %Zn, <vscale x 8 x half> %Zm) { ---------------- Nit: I would be a bit pedantic here and also check that they are used for the inline asm. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D66524/new/ https://reviews.llvm.org/D66524 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits