void updated this revision to Diff 244840.
void added a comment.
Use the BB when creating the MBB.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D69868/new/
https://reviews.llvm.org/D69868
Files:
llvm/docs/LangRef.rst
llvm/include/llvm/CodeGen/MachineBasicBlock.h
llvm/lib/AsmParser/LLParser.cpp
llvm/lib/CodeGen/MachineBasicBlock.cpp
llvm/lib/CodeGen/MachineVerifier.cpp
llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
llvm/lib/IR/Verifier.cpp
llvm/test/CodeGen/X86/callbr-asm-outputs.ll
llvm/test/CodeGen/X86/callbr-asm.ll
Index: llvm/test/CodeGen/X86/callbr-asm.ll
===================================================================
--- llvm/test/CodeGen/X86/callbr-asm.ll
+++ llvm/test/CodeGen/X86/callbr-asm.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=i686-- -O3 | FileCheck %s
+; RUN: llc < %s -mtriple=i686-- -O3 -verify-machineinstrs | FileCheck %s
; Tests for using callbr as an asm-goto wrapper
Index: llvm/test/CodeGen/X86/callbr-asm-outputs.ll
===================================================================
--- llvm/test/CodeGen/X86/callbr-asm-outputs.ll
+++ llvm/test/CodeGen/X86/callbr-asm-outputs.ll
@@ -1,18 +1,160 @@
-; RUN: not llc -mtriple=i686-- < %s 2> %t
-; RUN: FileCheck %s < %t
+; RUN: llc -mtriple=i686-- -verify-machineinstrs < %s | FileCheck %s
-; CHECK: error: asm-goto outputs not supported
+; A test for asm-goto output
-; A test for asm-goto output prohibition
-
-define i32 @test(i32 %a) {
+; CHECK-LABEL: test1:
+; CHECK: movl 4(%esp), %eax
+; CHECK-NEXT: addl $4, %eax
+; CHECK-NEXT: #APP
+; CHECK-NEXT: xorl %eax, %eax
+; CHECK-NEXT: jmp .Ltmp0
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB0_1:
+; CHECK-NEXT: retl
+; CHECK-LABEL: .Ltmp0: # Address of block that was removed by CodeGen
+define i32 @test1(i32 %x) {
entry:
- %0 = add i32 %a, 4
- %1 = callbr i32 asm "xorl $1, $1; jmp ${1:l}", "=&r,r,X,~{dirflag},~{fpsr},~{flags}"(i32 %0, i8* blockaddress(@test, %fail)) to label %normal [label %fail]
+ %add = add nsw i32 %x, 4
+ %ret = callbr i32 asm "xorl $1, $0; jmp ${2:l}", "=r,r,X,~{dirflag},~{fpsr},~{flags}"(i32 %add, i8* blockaddress(@test1, %abnormal))
+ to label %normal [label %abnormal]
normal:
- ret i32 %1
+ ret i32 %ret
-fail:
+abnormal:
ret i32 1
}
+
+; CHECK-LABEL: test2:
+; CHECK: # %bb.1: # %if.then
+; CHECK-NEXT: #APP
+; CHECK-NEXT: testl %esi, %esi
+; CHECK-NEXT: testl %edi, %esi
+; CHECK-NEXT: jne .Ltmp1
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB1_2:
+; CHECK-NEXT: jmp .LBB1_4
+; CHECK-NEXT: .LBB1_3: # %if.else
+; CHECK-NEXT: #APP
+; CHECK-NEXT: testl %esi, %edi
+; CHECK-NEXT: testl %esi, %edi
+; CHECK-NEXT: jne .Ltmp2
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB1_4:
+; CHECK-NEXT: movl %esi, %eax
+; CHECK-NEXT: addl %edi, %eax
+; CHECK-NEXT: .Ltmp2:
+; CHECK-NEXT: # %bb.5: # %return
+; CHECK-LABEL: .Ltmp1: # Address of block that was removed by CodeGen
+define i32 @test2(i32 %out1, i32 %out2) {
+entry:
+ %cmp = icmp slt i32 %out1, %out2
+ br i1 %cmp, label %if.then, label %if.else
+
+if.then: ; preds = %entry
+ %0 = callbr { i32, i32 } asm sideeffect "testl $0, $0; testl $1, $2; jne ${3:l}", "={si},={di},r,X,X,0,1,~{dirflag},~{fpsr},~{flags}"(i32 %out1, i8* blockaddress(@test2, %label_true), i8* blockaddress(@test2, %return), i32 %out1, i32 %out2)
+ to label %if.end [label %label_true, label %return]
+
+if.else: ; preds = %entry
+ %1 = callbr { i32, i32 } asm sideeffect "testl $0, $1; testl $2, $3; jne ${5:l}", "={si},={di},r,r,X,X,0,1,~{dirflag},~{fpsr},~{flags}"(i32 %out1, i32 %out2, i8* blockaddress(@test2, %label_true), i8* blockaddress(@test2, %return), i32 %out1, i32 %out2)
+ to label %if.end [label %label_true, label %return]
+
+if.end: ; preds = %if.else, %if.then
+ %.sink11 = phi { i32, i32 } [ %0, %if.then ], [ %1, %if.else ]
+ %asmresult3 = extractvalue { i32, i32 } %.sink11, 0
+ %asmresult4 = extractvalue { i32, i32 } %.sink11, 1
+ %add = add nsw i32 %asmresult4, %asmresult3
+ br label %return
+
+label_true: ; preds = %if.else, %if.then
+ br label %return
+
+return: ; preds = %if.then, %if.else, %label_true, %if.end
+ %retval.0 = phi i32 [ %add, %if.end ], [ -2, %label_true ], [ -1, %if.else ], [ -1, %if.then ]
+ ret i32 %retval.0
+}
+
+; CHECK-LABEL: test3:
+; CHECK: # %bb.1: # %true
+; CHECK-NEXT: #APP
+; CHECK-NEXT: .short %esi
+; CHECK-NEXT: .short %edi
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB2_2:
+; CHECK-NEXT: movl %edi, %eax
+; CHECK-NEXT: jmp .LBB2_5
+; CHECK-NEXT: .LBB2_3: # %false
+; CHECK-NEXT: #APP
+; CHECK-NEXT: .short %eax
+; CHECK-NEXT: .short %edx
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB2_4:
+; CHECK-NEXT: movl %edx, %eax
+; CHECK-NEXT: .LBB2_5: # %asm.fallthrough
+; CHECK-LABEL: .Ltmp3: # Address of block that was removed by CodeGen
+define i32 @test3(i1 %cmp) {
+entry:
+ br i1 %cmp, label %true, label %false
+
+true:
+ %0 = callbr { i32, i32 } asm sideeffect ".word $0, $1", "={si},={di},X" (i8* blockaddress(@test3, %indirect)) to label %asm.fallthrough [label %indirect]
+
+false:
+ %1 = callbr { i32, i32 } asm sideeffect ".word $0, $1", "={ax},={dx},X" (i8* blockaddress(@test3, %indirect)) to label %asm.fallthrough [label %indirect]
+
+asm.fallthrough:
+ %vals = phi { i32, i32 } [ %0, %true ], [ %1, %false ]
+ %v = extractvalue { i32, i32 } %vals, 1
+ ret i32 %v
+
+indirect:
+ ret i32 42
+}
+
+; Test 4 - asm-goto with output constraints.
+; CHECK-LABEL: test4:
+; CHECK: # %bb.0: # %entry
+; CHECK-NEXT: movl $-1, %eax
+; CHECK-NEXT: movl 4(%esp), %ecx
+; CHECK-NEXT: #APP
+; CHECK-NEXT: testl %ecx, %ecx
+; CHECK-NEXT: testl %edx, %ecx
+; CHECK-NEXT: jne .Ltmp4
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB3_1:
+; CHECK-NEXT: #APP
+; CHECK-NEXT: testl %ecx, %edx
+; CHECK-NEXT: testl %ecx, %edx
+; CHECK-NEXT: jne .Ltmp5
+; CHECK-NEXT: #NO_APP
+; CHECK-NEXT: .LBB3_2:
+; CHECK-NEXT: addl %edx, %ecx
+; CHECK-NEXT: movl %ecx, %eax
+; CHECK-NEXT: .Ltmp5:
+; CHECK-NEXT: # %bb.3: # %return
+; CHECK-NEXT: retl
+; CHECK-LABEL: .Ltmp4: # Address of block that was removed by CodeGen
+define i32 @test4(i32 %out1, i32 %out2) {
+entry:
+ %0 = callbr { i32, i32 } asm sideeffect "testl $0, $0; testl $1, $2; jne ${3:l}", "=r,=r,r,X,X,~{dirflag},~{fpsr},~{flags}"(i32 %out1, i8* blockaddress(@test4, %label_true), i8* blockaddress(@test4, %return))
+ to label %asm.fallthrough [label %label_true, label %return]
+
+asm.fallthrough: ; preds = %entry
+ %asmresult = extractvalue { i32, i32 } %0, 0
+ %asmresult1 = extractvalue { i32, i32 } %0, 1
+ %1 = callbr { i32, i32 } asm sideeffect "testl $0, $1; testl $2, $3; jne ${5:l}", "=r,=r,r,r,X,X,~{dirflag},~{fpsr},~{flags}"(i32 %asmresult, i32 %asmresult1, i8* blockaddress(@test4, %label_true), i8* blockaddress(@test4, %return))
+ to label %asm.fallthrough2 [label %label_true, label %return]
+
+asm.fallthrough2: ; preds = %asm.fallthrough
+ %asmresult3 = extractvalue { i32, i32 } %1, 0
+ %asmresult4 = extractvalue { i32, i32 } %1, 1
+ %add = add nsw i32 %asmresult3, %asmresult4
+ br label %return
+
+label_true: ; preds = %asm.fallthrough, %entry
+ br label %return
+
+return: ; preds = %entry, %asm.fallthrough, %label_true, %asm.fallthrough2
+ %retval.0 = phi i32 [ %add, %asm.fallthrough2 ], [ -2, %label_true ], [ -1, %asm.fallthrough ], [ -1, %entry ]
+ ret i32 %retval.0
+}
Index: llvm/lib/IR/Verifier.cpp
===================================================================
--- llvm/lib/IR/Verifier.cpp
+++ llvm/lib/IR/Verifier.cpp
@@ -2536,8 +2536,6 @@
void Verifier::visitCallBrInst(CallBrInst &CBI) {
Assert(CBI.isInlineAsm(), "Callbr is currently only used for asm-goto!",
&CBI);
- Assert(CBI.getType()->isVoidTy(), "Callbr return value is not supported!",
- &CBI);
for (unsigned i = 0, e = CBI.getNumSuccessors(); i != e; ++i)
Assert(CBI.getSuccessor(i)->getType()->isLabelTy(),
"Callbr successors must all have pointer type!", &CBI);
Index: llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
+++ llvm/lib/CodeGen/SelectionDAG/SelectionDAGBuilder.cpp
@@ -2864,15 +2864,18 @@
assert(isa<InlineAsm>(I.getCalledValue()) &&
"Only know how to handle inlineasm callbr");
visitInlineAsm(&I);
+ CopyToExportRegsIfNeeded(&I);
// Retrieve successors.
MachineBasicBlock *Return = FuncInfo.MBBMap[I.getDefaultDest()];
+ Return->setInlineAsmBrDefaultTarget();
// Update successor info.
addSuccessorWithProb(CallBrMBB, Return);
for (unsigned i = 0, e = I.getNumIndirectDests(); i < e; ++i) {
MachineBasicBlock *Target = FuncInfo.MBBMap[I.getIndirectDest(i)];
addSuccessorWithProb(CallBrMBB, Target);
+ CallBrMBB->addInlineAsmBrIndirectTarget(Target);
}
CallBrMBB->normalizeSuccProbs();
@@ -8133,6 +8136,7 @@
unsigned ArgNo = 0; // ArgNo - The argument of the CallInst.
unsigned ResNo = 0; // ResNo - The result number of the next output.
+ unsigned NumMatchingOps = 0;
for (auto &T : TargetConstraints) {
ConstraintOperands.push_back(SDISelAsmOperandInfo(T));
SDISelAsmOperandInfo &OpInfo = ConstraintOperands.back();
@@ -8146,8 +8150,12 @@
// only in asm's.
const Instruction *I = CS.getInstruction();
if (isa<CallBrInst>(I) &&
- (ArgNo - 1) >= (cast<CallBrInst>(I)->getNumArgOperands() -
- cast<CallBrInst>(I)->getNumIndirectDests())) {
+ ArgNo - 1 >= (cast<CallBrInst>(I)->getNumArgOperands() -
+ cast<CallBrInst>(I)->getNumIndirectDests() -
+ NumMatchingOps) &&
+ (NumMatchingOps == 0 ||
+ ArgNo - 1 < (cast<CallBrInst>(I)->getNumArgOperands() -
+ NumMatchingOps))) {
const auto *BA = cast<BlockAddress>(OpInfo.CallOperandVal);
EVT VT = TLI.getValueType(DAG.getDataLayout(), BA->getType(), true);
OpInfo.CallOperand = DAG.getTargetBlockAddress(BA, VT);
@@ -8178,6 +8186,9 @@
OpInfo.ConstraintVT = MVT::Other;
}
+ if (OpInfo.hasMatchingInput())
+ ++NumMatchingOps;
+
if (!HasSideEffect)
HasSideEffect = OpInfo.hasMemory(TLI);
Index: llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
===================================================================
--- llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
+++ llvm/lib/CodeGen/SelectionDAG/ScheduleDAGSDNodes.cpp
@@ -1027,6 +1027,69 @@
}
}
+ // Split after an INLINEASM_BR block with outputs. This allows us to keep the
+ // copy to/from register instructions from being between two terminator
+ // instructions, which causes the machine instruction verifier agita.
+ auto TI = llvm::find_if(*BB, [](const MachineInstr &MI){
+ return MI.getOpcode() == TargetOpcode::INLINEASM_BR;
+ });
+ auto SplicePt = TI != BB->end() ? std::next(TI) : BB->end();
+ if (TI != BB->end() && SplicePt != BB->end() &&
+ TI->getOpcode() == TargetOpcode::INLINEASM_BR &&
+ SplicePt->getOpcode() == TargetOpcode::COPY) {
+ MachineBasicBlock *FallThrough = BB->getFallThrough();
+ if (!FallThrough)
+ for (const MachineOperand &MO : BB->back().operands())
+ if (MO.isMBB()) {
+ FallThrough = MO.getMBB();
+ break;
+ }
+ assert(FallThrough && "Cannot find default dest block for callbr!");
+
+ MachineBasicBlock *CopyBB = MF.CreateMachineBasicBlock(BB->getBasicBlock());
+ MachineFunction::iterator BBI(*BB);
+ MF.insert(++BBI, CopyBB);
+
+ CopyBB->splice(CopyBB->begin(), BB, SplicePt, BB->end());
+ CopyBB->setInlineAsmBrDefaultTarget();
+
+ CopyBB->addSuccessor(FallThrough, BranchProbability::getOne());
+ BB->addSuccessor(CopyBB, BranchProbability::getOne());
+
+ // Mark all physical registers defined in the original block as being live
+ // on entry to the copy block.
+ for (const auto &MI : *CopyBB)
+ for (const MachineOperand &MO : MI.operands())
+ if (MO.isReg()) {
+ Register reg = MO.getReg();
+ if (Register::isPhysicalRegister(reg)) {
+ CopyBB->addLiveIn(reg);
+ break;
+ }
+ }
+
+ // Bit of a hack: The copy block we created here exists only because we want
+ // the CFG to work with the current system. However, the successors to the
+ // block with the INLINEASM_BR instruction expect values to come from *that*
+ // block, not this usurper block. Thus we steal its successors and add them
+ // to the copy so that everyone is happy.
+ for (auto *Succ : BB->successors())
+ if (Succ != CopyBB && !CopyBB->isSuccessor(Succ))
+ CopyBB->addSuccessor(Succ, BranchProbability::getZero());
+
+ for (auto *Succ : CopyBB->successors())
+ if (BB->isSuccessor(Succ))
+ BB->removeSuccessor(Succ);
+
+ CopyBB->normalizeSuccProbs();
+ BB->normalizeSuccProbs();
+
+ BB->transferInlineAsmBrIndirectTargets(CopyBB);
+
+ InsertPos = CopyBB->end();
+ return CopyBB;
+ }
+
InsertPos = Emitter.getInsertPos();
return Emitter.getBlock();
}
Index: llvm/lib/CodeGen/MachineVerifier.cpp
===================================================================
--- llvm/lib/CodeGen/MachineVerifier.cpp
+++ llvm/lib/CodeGen/MachineVerifier.cpp
@@ -621,6 +621,7 @@
// it is an entry block or landing pad.
for (const auto &LI : MBB->liveins()) {
if (isAllocatable(LI.PhysReg) && !MBB->isEHPad() &&
+ !MBB->isInlineAsmBrDefaultTarget() &&
MBB->getIterator() != MBB->getParent()->begin()) {
report("MBB has allocatable live-in, but isn't entry or landing-pad.", MBB);
report_context(LI.PhysReg);
@@ -629,17 +630,30 @@
}
// Count the number of landing pad successors.
- SmallPtrSet<MachineBasicBlock*, 4> LandingPadSuccs;
- for (MachineBasicBlock::const_succ_iterator I = MBB->succ_begin(),
- E = MBB->succ_end(); I != E; ++I) {
- if ((*I)->isEHPad())
- LandingPadSuccs.insert(*I);
- if (!FunctionBlocks.count(*I))
+ SmallPtrSet<const MachineBasicBlock*, 4> LandingPadSuccs;
+ for (const auto *succ : MBB->successors()) {
+ if (succ->isEHPad())
+ LandingPadSuccs.insert(succ);
+ if (!FunctionBlocks.count(succ))
report("MBB has successor that isn't part of the function.", MBB);
- if (!MBBInfoMap[*I].Preds.count(MBB)) {
+ if (!MBBInfoMap[succ].Preds.count(MBB)) {
report("Inconsistent CFG", MBB);
errs() << "MBB is not in the predecessor list of the successor "
- << printMBBReference(*(*I)) << ".\n";
+ << printMBBReference(*succ) << ".\n";
+ }
+ }
+
+ // Count the number of INLINEASM_BR indirect target successors.
+ SmallPtrSet<const MachineBasicBlock*, 4> IndirectTargetSuccs;
+ for (const auto *succ : MBB->successors()) {
+ if (MBB->isInlineAsmBrIndirectTarget(succ))
+ IndirectTargetSuccs.insert(succ);
+ if (!FunctionBlocks.count(succ))
+ report("MBB has successor that isn't part of the function.", MBB);
+ if (!MBBInfoMap[succ].Preds.count(MBB)) {
+ report("Inconsistent CFG", MBB);
+ errs() << "MBB is not in the predecessor list of the successor "
+ << printMBBReference(*succ) << ".\n";
}
}
@@ -680,11 +694,15 @@
// It's possible that the block legitimately ends with a noreturn
// call or an unreachable, in which case it won't actually fall
// out the bottom of the function.
- } else if (MBB->succ_size() == LandingPadSuccs.size()) {
+ } else if (MBB->succ_size() == LandingPadSuccs.size() ||
+ MBB->succ_size() == IndirectTargetSuccs.size()) {
// It's possible that the block legitimately ends with a noreturn
// call or an unreachable, in which case it won't actually fall
// out of the block.
- } else if (MBB->succ_size() != 1+LandingPadSuccs.size()) {
+ } else if ((LandingPadSuccs.size() &&
+ MBB->succ_size() != 1 + LandingPadSuccs.size()) ||
+ (IndirectTargetSuccs.size() &&
+ MBB->succ_size() != 1 + IndirectTargetSuccs.size())) {
report("MBB exits via unconditional fall-through but doesn't have "
"exactly one CFG successor!", MBB);
} else if (!MBB->isSuccessor(&*MBBI)) {
@@ -706,7 +724,10 @@
// landingpad, accept it as valid control flow.
if (MBB->succ_size() != 1+LandingPadSuccs.size() &&
(MBB->succ_size() != 1 || LandingPadSuccs.size() != 1 ||
- *MBB->succ_begin() != *LandingPadSuccs.begin())) {
+ *MBB->succ_begin() != *LandingPadSuccs.begin()) &&
+ MBB->succ_size() != 1 + IndirectTargetSuccs.size() &&
+ (MBB->succ_size() != 1 || IndirectTargetSuccs.size() != 1 ||
+ *MBB->succ_begin() != *IndirectTargetSuccs.begin())) {
report("MBB exits via unconditional branch but doesn't have "
"exactly one CFG successor!", MBB);
} else if (!MBB->isSuccessor(TBB)) {
Index: llvm/lib/CodeGen/MachineBasicBlock.cpp
===================================================================
--- llvm/lib/CodeGen/MachineBasicBlock.cpp
+++ llvm/lib/CodeGen/MachineBasicBlock.cpp
@@ -1113,8 +1113,12 @@
if (Succ->isEHPad())
return false;
- const MachineFunction *MF = getParent();
+ // Splitting the critical edge to a callbr's indirect block isn't advised.
+ // Don't do it in this generic function.
+ if (isInlineAsmBrIndirectTarget(Succ))
+ return false;
+ const MachineFunction *MF = getParent();
// Performance might be harmed on HW that implements branching using exec mask
// where both sides of the branches are always executed.
if (MF->getTarget().requiresStructuredCFG())
Index: llvm/lib/AsmParser/LLParser.cpp
===================================================================
--- llvm/lib/AsmParser/LLParser.cpp
+++ llvm/lib/AsmParser/LLParser.cpp
@@ -6420,9 +6420,6 @@
/*IsCall=*/true))
return true;
- if (isa<InlineAsm>(Callee) && !Ty->getReturnType()->isVoidTy())
- return Error(RetTypeLoc, "asm-goto outputs not supported");
-
// Set up the Attribute for the function.
SmallVector<Value *, 8> Args;
SmallVector<AttributeSet, 8> ArgAttrs;
Index: llvm/include/llvm/CodeGen/MachineBasicBlock.h
===================================================================
--- llvm/include/llvm/CodeGen/MachineBasicBlock.h
+++ llvm/include/llvm/CodeGen/MachineBasicBlock.h
@@ -130,6 +130,12 @@
/// Indicate that this basic block is the entry block of a cleanup funclet.
bool IsCleanupFuncletEntry = false;
+ /// Default target of the callbr of a basic block.
+ bool InlineAsmBrDefaultTarget = false;
+
+ /// List of indirect targets of the callbr of a basic block.
+ SmallPtrSet<const MachineBasicBlock*, 4> InlineAsmBrIndirectTargets;
+
/// since getSymbol is a relatively heavy-weight operation, the symbol
/// is only computed once and is cached.
mutable MCSymbol *CachedMCSymbol = nullptr;
@@ -409,6 +415,33 @@
/// Indicates if this is the entry block of a cleanup funclet.
void setIsCleanupFuncletEntry(bool V = true) { IsCleanupFuncletEntry = V; }
+ /// Returns true if this is the indirect dest of an INLINEASM_BR.
+ bool isInlineAsmBrIndirectTarget(const MachineBasicBlock *Tgt) const {
+ return InlineAsmBrIndirectTargets.count(Tgt);
+ }
+
+ /// Indicates if this is the indirect dest of an INLINEASM_BR.
+ void addInlineAsmBrIndirectTarget(const MachineBasicBlock *Tgt) {
+ InlineAsmBrIndirectTargets.insert(Tgt);
+ }
+
+ /// Transfers indirect targets to INLINEASM_BR's copy block.
+ void transferInlineAsmBrIndirectTargets(MachineBasicBlock *CopyBB) {
+ for (auto *Target : InlineAsmBrIndirectTargets)
+ CopyBB->addInlineAsmBrIndirectTarget(Target);
+ return InlineAsmBrIndirectTargets.clear();
+ }
+
+ /// Returns true if this is the default dest of an INLINEASM_BR.
+ bool isInlineAsmBrDefaultTarget() const {
+ return InlineAsmBrDefaultTarget;
+ }
+
+ /// Indicates if this is the default deft of an INLINEASM_BR.
+ void setInlineAsmBrDefaultTarget() {
+ InlineAsmBrDefaultTarget = true;
+ }
+
/// Returns true if it is legal to hoist instructions into this block.
bool isLegalToHoistInto() const;
Index: llvm/docs/LangRef.rst
===================================================================
--- llvm/docs/LangRef.rst
+++ llvm/docs/LangRef.rst
@@ -7211,14 +7211,14 @@
::
<result> = callbr [cconv] [ret attrs] [addrspace(<num>)] <ty>|<fnty> <fnptrval>(<function args>) [fn attrs]
- [operand bundles] to label <normal label> [other labels]
+ [operand bundles] to label <fallthrough label> [indirect labels]
Overview:
"""""""""
The '``callbr``' instruction causes control to transfer to a specified
function, with the possibility of control flow transfer to either the
-'``normal``' label or one of the '``other``' labels.
+'``fallthrough``' label or one of the '``indirect``' labels.
This instruction should only be used to implement the "goto" feature of gcc
style inline assembly. Any other usage is an error in the IR verifier.
@@ -7245,17 +7245,17 @@
type can be omitted if the function is not varargs.
#. '``fnptrval``': An LLVM value containing a pointer to a function to
be called. In most cases, this is a direct function call, but
- indirect ``callbr``'s are just as possible, calling an arbitrary pointer
+ other ``callbr``'s are just as possible, calling an arbitrary pointer
to function value.
#. '``function args``': argument list whose types match the function
signature argument types and parameter attributes. All arguments must
be of :ref:`first class <t_firstclass>` type. If the function signature
indicates the function accepts a variable number of arguments, the
extra arguments can be specified.
-#. '``normal label``': the label reached when the called function
- executes a '``ret``' instruction.
-#. '``other labels``': the labels reached when a callee transfers control
- to a location other than the normal '``normal label``'. The blockaddress
+#. '``fallthrough label``': the label reached when the inline assembly's
+ execution exits the bottom.
+#. '``indirect labels``': the labels reached when a callee transfers control
+ to a location other than the '``fallthrough label``'. The blockaddress
constant for these should also be in the list of '``function args``'.
#. The optional :ref:`function attributes <fnattrs>` list.
#. The optional :ref:`operand bundles <opbundles>` list.
@@ -7268,6 +7268,10 @@
establishes an association with additional labels to define where control
flow goes after the call.
+Outputs of a '``callbr``' instruction are valid only on the '``fallthrough``'
+path. Use of outputs on the '``indirect``' path(s) results in :ref:`poison
+values <poisonvalues>`.
+
The only use of this today is to implement the "goto" feature of gcc inline
assembly where additional labels can be provided as locations for the inline
assembly to jump to.
@@ -7275,10 +7279,15 @@
Example:
""""""""
-.. code-block:: text
+.. code-block:: llvm
- callbr void asm "", "r,x"(i32 %x, i8 *blockaddress(@foo, %fail))
- to label %normal [label %fail]
+ ; "asm goto" without output constraints.
+ callbr void asm "", "r,X"(i32 %x, i8 *blockaddress(@foo, %indirect))
+ to label %fallthrough [label %indirect]
+
+ ; "asm goto" with output constraints.
+ <result> = callbr i32 asm "", "=r,r,X"(i32 %x, i8 *blockaddress(@foo, %indirect))
+ to label %fallthrough [label %indirect]
.. _i_resume:
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