rjmccall added a comment. In D75169#1928696 <https://reviews.llvm.org/D75169#1928696>, @pratlucas wrote:
> > Oh, wait, AAPCS wants half values to be passed in the *least* significant > > bits of a GPR, even on big-endian machines? That's certainly more > > convenient, but it's a weird inconsistency with the otherwise iron rule of > > the calling convention, which that it's exactly as if you laid all of the > > arguments out in memory and then popped the first four 32-bit values off. > > We're talking about a calling convention here that literally skips > > registers in order to "align" arguments. > > > > Can we not just coerce to i16? Will LLVM not pass an i16 in the > > least-significant bits of a register? > > Yes, AAPCS specifies that they should go into the LSBs: > > > B.2 [...] If the argument is a Half-precision Floating Point Type its size > > is set to 4 bytes as if it had been copied to the least significant bits of > > a 32-bit register and the remaining bits filled with unspecified values. > > Coercing to i16 solves it for the general case, when the argumetns are going > into GPRs, but is not suficient when those arguments are required to go into > FP registers - e.g. `-mfloat-abi=hard`. Why not just make `half` as an argument do the right thing for that case? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D75169/new/ https://reviews.llvm.org/D75169 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
