dmgreen added inline comments.
================ Comment at: llvm/lib/Target/AArch64/AArch64InstrFormats.td:8055 multiclass SIMDFPIndexedTiedPatterns<string INST, SDPatternOperator OpNode> { + let Predicates = [HasNEON, HasFullFP16] in { + // 1 variant for the .8h version: DUPLANE from 128-bit ---------------- ilinpv wrote: > dmgreen wrote: > > Should we have equal patterns to those below for f32 as well? So using DUP, > > D vector (4xf16) and possibly from a vector_extract too. > I'm worried about performance impact of change fmadd/sub -> fmla/ls in last > pattern case. What performance impact are you worried about? ================ Comment at: llvm/lib/Target/AArch64/AArch64InstrFormats.td:8077 + + def : Pat<(f16 (OpNode (f16 FPR16:$Rd), (f16 FPR16:$Rn), + (vector_extract (v8f16 V128:$Rm), VectorIndexS:$idx))), ---------------- Do you mean the v4f16 variant of this pattern? Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D78252/new/ https://reviews.llvm.org/D78252 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits