efriedma accepted this revision. efriedma added inline comments.
================ Comment at: clang/include/clang/Basic/arm_sve.td:1249 +def SVSUDOT_S : SInst<"svsudot[_s32]", "ddqb", "i", MergeNone, "aarch64_sve_usdot", [ReverseUSDOT]>; +def SVSUDOT_N_S : SInst<"svsudot[_n_s32]", "ddq@", "i", MergeNone, "aarch64_sve_usdot", [ReverseUSDOT]>; + ---------------- fpetrogalli wrote: > fpetrogalli wrote: > > efriedma wrote: > > > These intrinsics aren't overloaded; maybe consider writing the actual > > > type int8_t/uint8_t, instead of introducing "unsigned scalar of 1/4 width > > > element type"? If there's some reason the current form is better, that's > > > fine, though. > > I am probably missing something, but I can't see a type specifier that is > > not overloaded and that renders to 8-bit elements? > > > > I have opted for adding "unsigned scalar of 1/4 width element type" because > > it keeps things symmetric with the vector equivalent, signed and unsigned. > > > > ``` > > // r: scalar of 1/4 width element type (splat to vector type) > > // @: unsigned scalar of 1/4 width element type (splat to vector type) > > [..] > > // b: 1/4 width unsigned elements, 4x element count > > // q: 1/4 width elements, 4x element count > > ``` > @efriedma , are you satisfied with this answer? are you happy for me to > submit this as it is? Yes, it's fine. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D79877/new/ https://reviews.llvm.org/D79877 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
