amyk updated this revision to Diff 274679.
amyk edited the summary of this revision.
amyk added a parent revision: D82584: [PowerPC][Power10] Exploit the High Order
Vector Multiply Instructions on Power10.
amyk added a comment.
Rebased patch.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D82576/new/
https://reviews.llvm.org/D82576
Files:
clang/lib/Headers/altivec.h
clang/test/CodeGen/builtins-ppc-p10vector.c
Index: clang/test/CodeGen/builtins-ppc-p10vector.c
===================================================================
--- clang/test/CodeGen/builtins-ppc-p10vector.c
+++ clang/test/CodeGen/builtins-ppc-p10vector.c
@@ -8,11 +8,73 @@
vector signed char vsca;
vector unsigned char vuca, vucb, vucc;
vector unsigned short vusa, vusb, vusc;
+vector signed int vsia, vsib;
vector unsigned int vuia, vuib, vuic;
+vector signed long long vslla, vsllb;
vector unsigned long long vulla, vullb, vullc;
vector unsigned __int128 vui128a, vui128b, vui128c;
unsigned int uia;
+vector signed long long test_vec_mul_sll(void) {
+ // CHECK: mul <2 x i64>
+ // CHECK-NEXT: ret <2 x i64>
+ return vec_mul(vslla, vsllb);
+}
+
+vector unsigned long long test_vec_mul_ull(void) {
+ // CHECK: mul <2 x i64>
+ // CHECK-NEXT: ret <2 x i64>
+ return vec_mul(vulla, vullb);
+}
+
+vector signed int test_vec_div_si(void) {
+ // CHECK: sdiv <4 x i32>
+ // CHECK-NEXT: ret <4 x i32>
+ return vec_div(vsia, vsib);
+}
+
+vector unsigned int test_vec_div_ui(void) {
+ // CHECK: udiv <4 x i32>
+ // CHECK-NEXT: ret <4 x i32>
+ return vec_div(vuia, vuib);
+}
+
+vector signed long long test_vec_div_sll(void) {
+ // CHECK: sdiv <2 x i64>
+ // CHECK-NEXT: ret <2 x i64>
+ return vec_div(vslla, vsllb);
+}
+
+vector unsigned long long test_vec_div_ull(void) {
+ // CHECK: udiv <2 x i64>
+ // CHECK-NEXT: ret <2 x i64>
+ return vec_div(vulla, vullb);
+}
+
+vector signed int test_vec_mod_si(void) {
+ // CHECK: srem <4 x i32>
+ // CHECK-NEXT: ret <4 x i32>
+ return vec_mod(vsia, vsib);
+}
+
+vector unsigned int test_vec_mod_ui(void) {
+ // CHECK: urem <4 x i32>
+ // CHECK-NEXT: ret <4 x i32>
+ return vec_mod(vuia, vuib);
+}
+
+vector signed long long test_vec_mod_sll(void) {
+ // CHECK: srem <2 x i64>
+ // CHECK-NEXT: ret <2 x i64>
+ return vec_mod(vslla, vsllb);
+}
+
+vector unsigned long long test_vec_mod_ull(void) {
+ // CHECK: urem <2 x i64>
+ // CHECK-NEXT: ret <2 x i64>
+ return vec_mod(vulla, vullb);
+}
+
vector unsigned long long test_vpdepd(void) {
// CHECK: @llvm.ppc.altivec.vpdepd(<2 x i64>
// CHECK-NEXT: ret <2 x i64>
Index: clang/lib/Headers/altivec.h
===================================================================
--- clang/lib/Headers/altivec.h
+++ clang/lib/Headers/altivec.h
@@ -16881,6 +16881,28 @@
return __builtin_altivec_vctzdm(__a, __b);
}
+/* vec_mod */
+
+static __inline__ vector signed int __ATTRS_o_ai
+vec_mod(vector signed int __a, vector signed int __b) {
+ return __a % __b;
+}
+
+static __inline__ vector unsigned int __ATTRS_o_ai
+vec_mod(vector unsigned int __a, vector unsigned int __b) {
+ return __a % __b;
+}
+
+static __inline__ vector signed long long __ATTRS_o_ai
+vec_mod(vector signed long long __a, vector signed long long __b) {
+ return __a % __b;
+}
+
+static __inline__ vector unsigned long long __ATTRS_o_ai
+vec_mod(vector unsigned long long __a, vector unsigned long long __b) {
+ return __a % __b;
+}
+
#endif /* __POWER10_VECTOR__ */
#undef __ATTRS_o_ai
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