fpallares added inline comments.
================ Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:2362 + } + if (TargetFlags & RISCV::VMConstraint) { + // vadc, vsbc are special cases. ---------------- Given that this constraint has no effect when `DestReg != RISCV::V0`, we could simplify the logic by adding this to the condition: ``` if (TargetFlags & RISCV::VMConstraint && DestReg == RISCV::V0) { ``` Then the `DestReg` checks within the block can go away. ================ Comment at: llvm/lib/Target/RISCV/AsmParser/RISCVAsmParser.cpp:2386 + CheckReg = Inst.getOperand(3).getReg(); } + if (DestReg == CheckReg) ---------------- With the suggestion above, this could be further simplified to: ``` if ((TargetFlags & RISCV::OneInput && Inst.getNumOperands() == 3) || Inst.getNumOperands() == 4) return Error(Loc, "The destination vector register group cannot overlap" " the mask register."); ``` Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D80802/new/ https://reviews.llvm.org/D80802 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits