efriedma added a comment. In D83553#2151591 <https://reviews.llvm.org/D83553#2151591>, @sdesmalen wrote:
> In D83553#2148429 <https://reviews.llvm.org/D83553#2148429>, @efriedma wrote: > > > > If you mean alloca's for single vectors > > > > I was really referring to the IR values themselves, not the memory > > representation. Since the width of the vectors is known, you could emit IR > > without any mention of scalable types at all (assuming the backend was > > extended to handle the intrinsics). > > > That's right, the reason is because codegen of the intrinsics currently only > works on scalable types. By casting the pointer to a vscale-pointer, all IR > values are always scalable so we don't need to worry about doing things like > reinterpet_cast from a scalable to fixed-width vector, or vice versa. I guess that's reasonable. I suspect we're eventually going to end up with that functionality anyway, but maybe not right now. ================ Comment at: clang/lib/CodeGen/CodeGenTypes.h:138 + llvm::Type *ConvertTypeForMem(QualType T, bool ForBitField = false, + bool EnforceFixedLengthSVEAttribute = false); ---------------- The default for EnforceFixedLengthSVEAttribute seems backwards; I would expect that almost everywhere that calls ConvertTypeForMem actually wants the fixed-length type. The scalable type only exists in registers. CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83553/new/ https://reviews.llvm.org/D83553 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
