amyk added inline comments.
================ Comment at: llvm/lib/Target/PowerPC/PPC.td:243 + "32Byte load and store instructions", + [FeatureISA3_0]>; ---------------- Is this supposed to be `FeatureISA3_1`? ================ Comment at: llvm/lib/Target/PowerPC/PPCScheduleP9.td:44 // Do not support QPX (Quad Processing eXtension), SPE (Signal Processing // Engine), prefixed instructions on Power 9, PC relative mem ops, or // instructions introduced in ISA 3.1. ---------------- Add the paired vector mem ops to the comment. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83722/new/ https://reviews.llvm.org/D83722 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
