nhaehnle marked 3 inline comments as done. nhaehnle added inline comments.
================ Comment at: llvm/include/llvm/CodeGen/MachineCfgTraits.h:44 + // use on a 32-bit architecture. + assert(wrapped != (uintptr_t)-1 && wrapped != (uintptr_t)-2); + ---------------- arsenm wrote: > I feel like there should be a better way to do this; we should probably have > an assert where virtual registers are created The reason for doing it here is that this is the place where the reinterpret happens. If the check is elsewhere, it's easy to miss by a user of this. ================ Comment at: llvm/include/llvm/CodeGen/MachineCfgTraits.h:101 + return nullptr; + return m_regInfo->getUniqueVRegDef(value)->getParent(); + } ---------------- arsenm wrote: > I think regular getVRegDef is preferable for SSA MIR Fixed locally. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D83088/new/ https://reviews.llvm.org/D83088 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
