This revision was landed with ongoing or failed builds. This revision was automatically updated to reflect the committed changes. Closed by commit rGc4e574323210: [PowerPC] Implement low-order Vector Modulus Builtins, and add Vector… (authored by amyk).
Changed prior to commit: https://reviews.llvm.org/D82576?vs=274679&id=282244#toc Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D82576/new/ https://reviews.llvm.org/D82576 Files: clang/lib/Headers/altivec.h clang/test/CodeGen/builtins-ppc-p10vector.c
Index: clang/test/CodeGen/builtins-ppc-p10vector.c =================================================================== --- clang/test/CodeGen/builtins-ppc-p10vector.c +++ clang/test/CodeGen/builtins-ppc-p10vector.c @@ -25,6 +25,66 @@ unsigned short usa; unsigned long long ulla; +vector signed long long test_vec_mul_sll(void) { + // CHECK: mul <2 x i64> + // CHECK-NEXT: ret <2 x i64> + return vec_mul(vslla, vsllb); +} + +vector unsigned long long test_vec_mul_ull(void) { + // CHECK: mul <2 x i64> + // CHECK-NEXT: ret <2 x i64> + return vec_mul(vulla, vullb); +} + +vector signed int test_vec_div_si(void) { + // CHECK: sdiv <4 x i32> + // CHECK-NEXT: ret <4 x i32> + return vec_div(vsia, vsib); +} + +vector unsigned int test_vec_div_ui(void) { + // CHECK: udiv <4 x i32> + // CHECK-NEXT: ret <4 x i32> + return vec_div(vuia, vuib); +} + +vector signed long long test_vec_div_sll(void) { + // CHECK: sdiv <2 x i64> + // CHECK-NEXT: ret <2 x i64> + return vec_div(vslla, vsllb); +} + +vector unsigned long long test_vec_div_ull(void) { + // CHECK: udiv <2 x i64> + // CHECK-NEXT: ret <2 x i64> + return vec_div(vulla, vullb); +} + +vector signed int test_vec_mod_si(void) { + // CHECK: srem <4 x i32> + // CHECK-NEXT: ret <4 x i32> + return vec_mod(vsia, vsib); +} + +vector unsigned int test_vec_mod_ui(void) { + // CHECK: urem <4 x i32> + // CHECK-NEXT: ret <4 x i32> + return vec_mod(vuia, vuib); +} + +vector signed long long test_vec_mod_sll(void) { + // CHECK: srem <2 x i64> + // CHECK-NEXT: ret <2 x i64> + return vec_mod(vslla, vsllb); +} + +vector unsigned long long test_vec_mod_ull(void) { + // CHECK: urem <2 x i64> + // CHECK-NEXT: ret <2 x i64> + return vec_mod(vulla, vullb); +} + vector unsigned long long test_vpdepd(void) { // CHECK: @llvm.ppc.altivec.vpdepd(<2 x i64> // CHECK-NEXT: ret <2 x i64> Index: clang/lib/Headers/altivec.h =================================================================== --- clang/lib/Headers/altivec.h +++ clang/lib/Headers/altivec.h @@ -16933,6 +16933,28 @@ return __builtin_altivec_vctzdm(__a, __b); } +/* vec_mod */ + +static __inline__ vector signed int __ATTRS_o_ai +vec_mod(vector signed int __a, vector signed int __b) { + return __a % __b; +} + +static __inline__ vector unsigned int __ATTRS_o_ai +vec_mod(vector unsigned int __a, vector unsigned int __b) { + return __a % __b; +} + +static __inline__ vector signed long long __ATTRS_o_ai +vec_mod(vector signed long long __a, vector signed long long __b) { + return __a % __b; +} + +static __inline__ vector unsigned long long __ATTRS_o_ai +vec_mod(vector unsigned long long __a, vector unsigned long long __b) { + return __a % __b; +} + /* vec_sldbi */ #define vec_sldb(__a, __b, __c) __builtin_altivec_vsldbi(__a, __b, (__c & 0x7))
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