arames updated this revision to Diff 295316.
arames added a comment.
Update commit message.
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rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D88265/new/
https://reviews.llvm.org/D88265
Files:
clang/lib/Sema/SemaExpr.cpp
clang/test/Sema/fp16vec-sema.c
Index: clang/test/Sema/fp16vec-sema.c
===================================================================
--- clang/test/Sema/fp16vec-sema.c
+++ clang/test/Sema/fp16vec-sema.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -fsyntax-only -verify %s
+// RUN: %clang_cc1 -fsyntax-only -Wno-unused-value -verify %s
typedef __fp16 half4 __attribute__ ((vector_size (8)));
typedef float float4 __attribute__ ((vector_size (16)));
@@ -28,6 +28,8 @@
sv0 = hv0 >= hv1;
sv0 = hv0 || hv1; // expected-error{{logical expression with vector types
'half4' (vector of 4 '__fp16' values) and 'half4' is only supported in C++}}
sv0 = hv0 && hv1; // expected-error{{logical expression with vector types
'half4' (vector of 4 '__fp16' values) and 'half4' is only supported in C++}}
+ hv0, 1;
+ 1, hv0;
// Implicit conversion between half vectors and float vectors are not
allowed.
hv0 = fv0; // expected-error{{assigning to}}
Index: clang/lib/Sema/SemaExpr.cpp
===================================================================
--- clang/lib/Sema/SemaExpr.cpp
+++ clang/lib/Sema/SemaExpr.cpp
@@ -13933,9 +13933,10 @@
// float vectors and truncating the result back to half vector. For now, we
do
// this only when HalfArgsAndReturn is set (that is, when the target is arm
or
// arm64).
- assert(isVector(RHS.get()->getType(), Context.HalfTy) ==
- isVector(LHS.get()->getType(), Context.HalfTy) &&
- "both sides are half vectors or neither sides are");
+ assert(
+ (Opc == BO_Comma || isVector(RHS.get()->getType(), Context.HalfTy) ==
+ isVector(LHS.get()->getType(), Context.HalfTy))
&&
+ "both sides are half vectors or neither sides are");
ConvertHalfVec =
needsConversionOfHalfVec(ConvertHalfVec, Context, LHS.get(), RHS.get());
Index: clang/test/Sema/fp16vec-sema.c
===================================================================
--- clang/test/Sema/fp16vec-sema.c
+++ clang/test/Sema/fp16vec-sema.c
@@ -1,4 +1,4 @@
-// RUN: %clang_cc1 -fsyntax-only -verify %s
+// RUN: %clang_cc1 -fsyntax-only -Wno-unused-value -verify %s
typedef __fp16 half4 __attribute__ ((vector_size (8)));
typedef float float4 __attribute__ ((vector_size (16)));
@@ -28,6 +28,8 @@
sv0 = hv0 >= hv1;
sv0 = hv0 || hv1; // expected-error{{logical expression with vector types 'half4' (vector of 4 '__fp16' values) and 'half4' is only supported in C++}}
sv0 = hv0 && hv1; // expected-error{{logical expression with vector types 'half4' (vector of 4 '__fp16' values) and 'half4' is only supported in C++}}
+ hv0, 1;
+ 1, hv0;
// Implicit conversion between half vectors and float vectors are not allowed.
hv0 = fv0; // expected-error{{assigning to}}
Index: clang/lib/Sema/SemaExpr.cpp
===================================================================
--- clang/lib/Sema/SemaExpr.cpp
+++ clang/lib/Sema/SemaExpr.cpp
@@ -13933,9 +13933,10 @@
// float vectors and truncating the result back to half vector. For now, we do
// this only when HalfArgsAndReturn is set (that is, when the target is arm or
// arm64).
- assert(isVector(RHS.get()->getType(), Context.HalfTy) ==
- isVector(LHS.get()->getType(), Context.HalfTy) &&
- "both sides are half vectors or neither sides are");
+ assert(
+ (Opc == BO_Comma || isVector(RHS.get()->getType(), Context.HalfTy) ==
+ isVector(LHS.get()->getType(), Context.HalfTy)) &&
+ "both sides are half vectors or neither sides are");
ConvertHalfVec =
needsConversionOfHalfVec(ConvertHalfVec, Context, LHS.get(), RHS.get());
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