bryanpkc added inline comments.
================
Comment at: llvm/lib/Target/AArch64/AArch64SchedTSV110.td:9
+//
+// This file defines the machine model for ARM Huawei TSV110 to support
+// instruction scheduling and other instruction cost heuristics.
----------------
I suggest deleting the word `ARM` here to avoid confusion.
================
Comment at: llvm/lib/Target/AArch64/AArch64SchedTSV110.td:28
+ list<Predicate> UnsupportedFeatures = !listconcat(SVEUnsupported.F,
+ PAUnsupported.F);
+}
----------------
Indent to align with the previous argument?
================
Comment at: llvm/lib/Target/AArch64/AArch64SchedTSV110.td:53
+
+//Integer ALU
+def : WriteRes<WriteImm, [TSV110UnitALUAB]> { let Latency = 1; }
----------------
Nit: Leave a space after the `//` delimiter.
================
Comment at: llvm/lib/Target/AArch64/AArch64SchedTSV110.td:128
+
+// Detailed Refinedments
+//===----------------------------------------------------------------------===//
----------------
Type: `Refinements`
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D89972/new/
https://reviews.llvm.org/D89972
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