steven.zhang added inline comments.
================ Comment at: llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp:418 + // should prefer D-form if LXVX / STXVX uses a ZERO or ZERO8 + if (MI.getOpcode() == PPC::LXVX || MI.getOpcode() == PPC::STXVX) { + LLVM_DEBUG(dbgs() << "Replacing LXVX/STXVX REG, 0 with LXV/STX\n"); ---------------- Some comments for current implementation. 1. Can we do this inside TII->convertToImmediateForm()? Notice that we have statistic data for such convert. Though it now handles x-load + addi -> d-load, it could be extended to handle x-load, 0 -> d-load. 2. I am not sure why just handle the lxvx. We have quite a lot x-form. ImmInstrInfo contains such information and can we query it to do the transformation instead of enum the opcode? ================ Comment at: llvm/lib/Target/PowerPC/PPCPreEmitPeephole.cpp:421 + // if it's Frame index we should not apply the transformation + if (!MI.getOperand(1).isFI() && + (MI.getOperand(1).getReg() == PPC::ZERO || ---------------- check isReg() Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D91279/new/ https://reviews.llvm.org/D91279 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits