HsiangKai updated this revision to Diff 316556.
HsiangKai added a comment.
Recover comments.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D92715/new/
https://reviews.llvm.org/D92715
Files:
clang/include/clang/AST/ASTContext.h
clang/include/clang/AST/Type.h
clang/include/clang/AST/TypeProperties.td
clang/include/clang/Basic/RISCVVTypes.def
clang/include/clang/Basic/TargetInfo.h
clang/include/clang/Serialization/ASTBitCodes.h
clang/include/clang/module.modulemap
clang/lib/AST/ASTContext.cpp
clang/lib/AST/ASTImporter.cpp
clang/lib/AST/ExprConstant.cpp
clang/lib/AST/ItaniumMangle.cpp
clang/lib/AST/MicrosoftMangle.cpp
clang/lib/AST/NSAPI.cpp
clang/lib/AST/PrintfFormatString.cpp
clang/lib/AST/Type.cpp
clang/lib/AST/TypeLoc.cpp
clang/lib/Basic/TargetInfo.cpp
clang/lib/Basic/Targets/RISCV.h
clang/lib/CodeGen/CGDebugInfo.cpp
clang/lib/CodeGen/CodeGenTypes.cpp
clang/lib/CodeGen/ItaniumCXXABI.cpp
clang/lib/Index/USRGeneration.cpp
clang/lib/Sema/Sema.cpp
clang/lib/Sema/SemaExpr.cpp
clang/lib/Serialization/ASTCommon.cpp
clang/lib/Serialization/ASTReader.cpp
clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
clang/test/Sema/riscv-types.c
clang/tools/libclang/CIndex.cpp
Index: clang/tools/libclang/CIndex.cpp
===================================================================
--- clang/tools/libclang/CIndex.cpp
+++ clang/tools/libclang/CIndex.cpp
@@ -1548,6 +1548,8 @@
#include "clang/Basic/AArch64SVEACLETypes.def"
#define PPC_VECTOR_TYPE(Name, Id, Size) case BuiltinType::Id:
#include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
#define BUILTIN_TYPE(Id, SingletonId)
#define SIGNED_TYPE(Id, SingletonId) case BuiltinType::Id:
#define UNSIGNED_TYPE(Id, SingletonId) case BuiltinType::Id:
Index: clang/test/Sema/riscv-types.c
===================================================================
--- /dev/null
+++ clang/test/Sema/riscv-types.c
@@ -0,0 +1,136 @@
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -ast-print %s \
+// RUN: | FileCheck %s
+
+void bar(void) {
+ // CHECK: __rvv_int64m1_t x0;
+ __rvv_int64m1_t x0;
+
+ // CHECK: __rvv_float64m1_t x1;
+ __rvv_float64m1_t x1;
+
+ // CHECK: __rvv_int64m2_t x2;
+ __rvv_int64m2_t x2;
+
+ // CHECK: __rvv_float64m2_t x3;
+ __rvv_float64m2_t x3;
+
+ // CHECK: __rvv_int64m4_t x4;
+ __rvv_int64m4_t x4;
+
+ // CHECK: __rvv_float64m4_t x5;
+ __rvv_float64m4_t x5;
+
+ // CHECK: __rvv_int64m8_t x6;
+ __rvv_int64m8_t x6;
+
+ // CHECK: __rvv_float64m8_t x7;
+ __rvv_float64m8_t x7;
+
+ // CHECK: __rvv_int32m1_t x8;
+ __rvv_int32m1_t x8;
+
+ // CHECK: __rvv_float32m1_t x9;
+ __rvv_float32m1_t x9;
+
+ // CHECK: __rvv_int32m2_t x10;
+ __rvv_int32m2_t x10;
+
+ // CHECK: __rvv_float32m2_t x11;
+ __rvv_float32m2_t x11;
+
+ // CHECK: __rvv_int32m4_t x12;
+ __rvv_int32m4_t x12;
+
+ // CHECK: __rvv_float32m4_t x13;
+ __rvv_float32m4_t x13;
+
+ // CHECK: __rvv_int32m8_t x14;
+ __rvv_int32m8_t x14;
+
+ // CHECK: __rvv_float32m8_t x15;
+ __rvv_float32m8_t x15;
+
+ // CHECK: __rvv_int16m1_t x16;
+ __rvv_int16m1_t x16;
+
+ // CHECK: __rvv_float16m1_t x17;
+ __rvv_float16m1_t x17;
+
+ // CHECK: __rvv_int16m2_t x18;
+ __rvv_int16m2_t x18;
+
+ // CHECK: __rvv_float16m2_t x19;
+ __rvv_float16m2_t x19;
+
+ // CHECK: __rvv_int16m4_t x20;
+ __rvv_int16m4_t x20;
+
+ // CHECK: __rvv_float16m4_t x21;
+ __rvv_float16m4_t x21;
+
+ // CHECK: __rvv_int16m8_t x22;
+ __rvv_int16m8_t x22;
+
+ // CHECK: __rvv_float16m8_t x23;
+ __rvv_float16m8_t x23;
+
+ // CHECK: __rvv_int8m1_t x24;
+ __rvv_int8m1_t x24;
+
+ // CHECK: __rvv_int8m2_t x25;
+ __rvv_int8m2_t x25;
+
+ // CHECK: __rvv_int8m4_t x26;
+ __rvv_int8m4_t x26;
+
+ // CHECK: __rvv_int8m8_t x27;
+ __rvv_int8m8_t x27;
+
+ // CHECK: __rvv_bool64_t x28;
+ __rvv_bool64_t x28;
+
+ // CHECK: __rvv_bool32_t x29;
+ __rvv_bool32_t x29;
+
+ // CHECK: __rvv_bool16_t x30;
+ __rvv_bool16_t x30;
+
+ // CHECK: __rvv_bool8_t x31;
+ __rvv_bool8_t x31;
+
+ // CHECK: __rvv_bool8_t x32;
+ __rvv_bool8_t x32;
+
+ // CHECK: __rvv_bool8_t x33;
+ __rvv_bool8_t x33;
+
+ // CHECK: __rvv_bool8_t x34;
+ __rvv_bool8_t x34;
+
+ // CHECK: __rvv_int32mf2_t x35;
+ __rvv_int32mf2_t x35;
+
+ // CHECK: __rvv_float32mf2_t x36;
+ __rvv_float32mf2_t x36;
+
+ // CHECK: __rvv_int16mf4_t x37;
+ __rvv_int16mf4_t x37;
+
+ // CHECK: __rvv_float16mf4_t x38;
+ __rvv_float16mf4_t x38;
+
+ // CHECK: __rvv_int16mf2_t x39;
+ __rvv_int16mf2_t x39;
+
+ // CHECK: __rvv_float16mf2_t x40;
+ __rvv_float16mf2_t x40;
+
+ // CHECK: __rvv_int8mf8_t x41;
+ __rvv_int8mf8_t x41;
+
+ // CHECK: __rvv_int8mf4_t x42;
+ __rvv_int8mf4_t x42;
+
+ // CHECK: __rvv_int8mf2_t x43;
+ __rvv_int8mf2_t x43;
+}
Index: clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
===================================================================
--- /dev/null
+++ clang/test/CodeGen/RISCV/riscv-v-debuginfo.c
@@ -0,0 +1,34 @@
+// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v \
+// RUN: -dwarf-version=4 -debug-info-kind=limited -emit-llvm -o - %s \
+// RUN: | FileCheck --check-prefix=DEBUGINFO %s
+#include <stdint.h>
+
+__rvv_int16m2_t f1(__rvv_int16m2_t arg_0, __rvv_int16m2_t arg_1, int64_t arg_2)
+{
+ __rvv_int16m2_t ret = __builtin_rvv_vadd_vv_i16m2_vl(arg_0, arg_1, arg_2);
+ return ret;
+}
+
+// DEBUGINFO: !14 = !DICompositeType(tag: DW_TAG_array_type, baseType: !15, flags: DIFlagVector, element
+// DEBUGINFO: s: !16)
+// DEBUGINFO: !16 = !{!17}
+// DEBUGINFO: !17 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, DW_OP_con
+// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_mul))
+
+__rvv_int16mf2_t f2(__rvv_int16mf2_t arg_0, __rvv_int16mf2_t arg_1, int64_t arg_2)
+{
+ __rvv_int16mf2_t ret = __builtin_rvv_vadd_vv_i16mf2_vl(arg_0, arg_1, arg_2);
+ return ret;
+}
+
+// DEBUGINFO: !41 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, DW_OP_con
+// DEBUGINFO: stu, 2, DW_OP_div, DW_OP_constu, 2, DW_OP_div))
+
+__rvv_int32mf2_t f3(__rvv_int32mf2_t arg_0, __rvv_int32mf2_t arg_1, int64_t arg_2)
+{
+ __rvv_int32mf2_t ret = __builtin_rvv_vadd_vv_i32mf2_vl(arg_0, arg_1, arg_2);
+ return ret;
+}
+
+// DEBUGINFO: !63 = !DISubrange(lowerBound: 0, upperBound: !DIExpression(DW_OP_bregx, 7202, 0, DW_OP_con
+// DEBUGINFO: stu, 4, DW_OP_div, DW_OP_constu, 2, DW_OP_div))
Index: clang/lib/Serialization/ASTReader.cpp
===================================================================
--- clang/lib/Serialization/ASTReader.cpp
+++ clang/lib/Serialization/ASTReader.cpp
@@ -7030,6 +7030,11 @@
T = Context.Id##Ty; \
break;
#include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) \
+ case PREDEF_TYPE_##Id##_ID: \
+ T = Context.SingletonId; \
+ break;
+#include "clang/Basic/RISCVVTypes.def"
}
assert(!T.isNull() && "Unknown predefined type");
Index: clang/lib/Serialization/ASTCommon.cpp
===================================================================
--- clang/lib/Serialization/ASTCommon.cpp
+++ clang/lib/Serialization/ASTCommon.cpp
@@ -242,6 +242,11 @@
ID = PREDEF_TYPE_##Id##_ID; \
break;
#include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) \
+ case BuiltinType::Id: \
+ ID = PREDEF_TYPE_##Id##_ID; \
+ break;
+#include "clang/Basic/RISCVVTypes.def"
case BuiltinType::BuiltinFn:
ID = PREDEF_TYPE_BUILTIN_FN;
break;
Index: clang/lib/Sema/SemaExpr.cpp
===================================================================
--- clang/lib/Sema/SemaExpr.cpp
+++ clang/lib/Sema/SemaExpr.cpp
@@ -6062,6 +6062,9 @@
#define PPC_VECTOR_TYPE(Name, Id, Size) \
case BuiltinType::Id:
#include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) \
+ case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
#define PLACEHOLDER_TYPE(ID, SINGLETON_ID)
#define BUILTIN_TYPE(ID, SINGLETON_ID) case BuiltinType::ID:
#include "clang/AST/BuiltinTypes.def"
@@ -19356,6 +19359,9 @@
#define PPC_VECTOR_TYPE(Name, Id, Size) \
case BuiltinType::Id:
#include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) \
+ case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
#define BUILTIN_TYPE(Id, SingletonId) case BuiltinType::Id:
#define PLACEHOLDER_TYPE(Id, SingletonId)
#include "clang/AST/BuiltinTypes.def"
Index: clang/lib/Sema/Sema.cpp
===================================================================
--- clang/lib/Sema/Sema.cpp
+++ clang/lib/Sema/Sema.cpp
@@ -383,6 +383,12 @@
#include "clang/Basic/PPCTypes.def"
}
+ if (Context.getTargetInfo().hasRISCVVTypes()) {
+#define RVV_TYPE(Name, Id, SingletonId) \
+ addImplicitTypedef(Name, Context.SingletonId);
+#include "clang/Basic/RISCVVTypes.def"
+ }
+
if (Context.getTargetInfo().hasBuiltinMSVaList()) {
DeclarationName MSVaList = &Context.Idents.get("__builtin_ms_va_list");
if (IdResolver.begin(MSVaList) == IdResolver.end())
Index: clang/lib/Index/USRGeneration.cpp
===================================================================
--- clang/lib/Index/USRGeneration.cpp
+++ clang/lib/Index/USRGeneration.cpp
@@ -732,6 +732,9 @@
#define PPC_VECTOR_TYPE(Name, Id, Size) \
case BuiltinType::Id:
#include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) \
+ case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
case BuiltinType::ShortAccum:
case BuiltinType::Accum:
case BuiltinType::LongAccum:
Index: clang/lib/CodeGen/ItaniumCXXABI.cpp
===================================================================
--- clang/lib/CodeGen/ItaniumCXXABI.cpp
+++ clang/lib/CodeGen/ItaniumCXXABI.cpp
@@ -3181,6 +3181,9 @@
#define PPC_VECTOR_TYPE(Name, Id, Size) \
case BuiltinType::Id:
#include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) \
+ case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
case BuiltinType::ShortAccum:
case BuiltinType::Accum:
case BuiltinType::LongAccum:
Index: clang/lib/CodeGen/CodeGenTypes.cpp
===================================================================
--- clang/lib/CodeGen/CodeGenTypes.cpp
+++ clang/lib/CodeGen/CodeGenTypes.cpp
@@ -601,7 +601,17 @@
llvm::FixedVectorType::get(ConvertType(Context.BoolTy), Size); \
break;
#include "clang/Basic/PPCTypes.def"
- case BuiltinType::Dependent:
+#define RVV_TYPE(Name, Id, SingletonId) \
+ case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
+ {
+ ASTContext::BuiltinVectorTypeInfo Info =
+ Context.getBuiltinVectorTypeInfo(cast<BuiltinType>(Ty));
+ return llvm::ScalableVectorType::get(ConvertType(Info.ElementType),
+ Info.EC.getKnownMinValue() *
+ Info.NumVectors);
+ }
+ case BuiltinType::Dependent:
#define BUILTIN_TYPE(Id, SingletonId)
#define PLACEHOLDER_TYPE(Id, SingletonId) \
case BuiltinType::Id:
Index: clang/lib/CodeGen/CGDebugInfo.cpp
===================================================================
--- clang/lib/CodeGen/CGDebugInfo.cpp
+++ clang/lib/CodeGen/CGDebugInfo.cpp
@@ -760,6 +760,63 @@
#include "clang/Basic/PPCTypes.def"
return CreateType(cast<const BuiltinType>(CGM.getContext().IntTy));
+#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
+ {
+ ASTContext::BuiltinVectorTypeInfo Info =
+ CGM.getContext().getBuiltinVectorTypeInfo(BT);
+
+ unsigned ElementCount = Info.EC.getKnownMinValue();
+ unsigned SEW = CGM.getContext().getTypeSize(Info.ElementType);
+
+ bool Fractional;
+ unsigned LMUL;
+ unsigned FixedSize = ElementCount * SEW;
+ // In RVV scalable vector types, we encode 64 bits in the fixed part.
+ if (FixedSize < 64) {
+ Fractional = true;
+ LMUL = 64 / FixedSize;
+ } else {
+ Fractional = false;
+ LMUL = FixedSize / 64;
+ }
+ // Mask type only occupies one vector register.
+ if (Info.ElementType == CGM.getContext().BoolTy) {
+ Fractional = false;
+ LMUL = 1;
+ }
+
+ // Element count = (VLENB / SEW) x LMUL
+ SmallVector<int64_t, 9> Expr(
+ // The DW_OP_bregx operation has two operands: a register which is
+ // specified by an unsigned LEB128 number, followed by a signed LEB128
+ // offset.
+ {llvm::dwarf::DW_OP_bregx, // Read the contents of a register.
+ 4096 + 0xC22, // RISC-V VLENB CSR register.
+ 0, // Offset for DW_OP_bregx. It is dummy here.
+ llvm::dwarf::DW_OP_constu,
+ SEW / 8, // SEW is in bits.
+ llvm::dwarf::DW_OP_div,
+ llvm::dwarf::DW_OP_constu,
+ LMUL});
+ if (Fractional)
+ Expr.push_back(llvm::dwarf::DW_OP_div);
+ else
+ Expr.push_back(llvm::dwarf::DW_OP_mul);
+
+ auto *LowerBound =
+ llvm::ConstantAsMetadata::get(llvm::ConstantInt::getSigned(
+ llvm::Type::getInt64Ty(CGM.getLLVMContext()), 0));
+ auto *UpperBound = DBuilder.createExpression(Expr);
+ llvm::Metadata *Subscript = DBuilder.getOrCreateSubrange(
+ /*count*/ nullptr, LowerBound, UpperBound, /*stride*/ nullptr);
+ llvm::DINodeArray SubscriptArray = DBuilder.getOrCreateArray(Subscript);
+ llvm::DIType *ElemTy =
+ getOrCreateType(Info.ElementType, TheCU->getFile());
+
+ auto Align = getTypeAlignIfRequired(BT, CGM.getContext());
+ return DBuilder.createVectorType(/*Size=*/0, Align, ElemTy, SubscriptArray);
+ }
case BuiltinType::UChar:
case BuiltinType::Char_U:
Encoding = llvm::dwarf::DW_ATE_unsigned_char;
Index: clang/lib/Basic/Targets/RISCV.h
===================================================================
--- clang/lib/Basic/Targets/RISCV.h
+++ clang/lib/Basic/Targets/RISCV.h
@@ -43,6 +43,7 @@
SuitableAlign = 128;
WCharType = SignedInt;
WIntType = UnsignedInt;
+ HasRISCVVTypes = true;
}
bool setCPU(const std::string &Name) override {
Index: clang/lib/Basic/TargetInfo.cpp
===================================================================
--- clang/lib/Basic/TargetInfo.cpp
+++ clang/lib/Basic/TargetInfo.cpp
@@ -115,6 +115,7 @@
HasBuiltinMSVaList = false;
IsRenderScriptTarget = false;
HasAArch64SVETypes = false;
+ HasRISCVVTypes = false;
AllowAMDGPUUnsafeFPAtomics = false;
ARMCDECoprocMask = 0;
Index: clang/lib/AST/TypeLoc.cpp
===================================================================
--- clang/lib/AST/TypeLoc.cpp
+++ clang/lib/AST/TypeLoc.cpp
@@ -406,6 +406,9 @@
#define PPC_VECTOR_TYPE(Name, Id, Size) \
case BuiltinType::Id:
#include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) \
+ case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
case BuiltinType::BuiltinFn:
case BuiltinType::IncompleteMatrixIdx:
case BuiltinType::OMPArraySection:
Index: clang/lib/AST/Type.cpp
===================================================================
--- clang/lib/AST/Type.cpp
+++ clang/lib/AST/Type.cpp
@@ -2279,6 +2279,8 @@
// SVE Types
#define SVE_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
#include "clang/Basic/AArch64SVEACLETypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
return true;
default:
return false;
@@ -3088,6 +3090,10 @@
case Id: \
return #Name;
#include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) \
+ case Id: \
+ return Name;
+#include "clang/Basic/RISCVVTypes.def"
}
llvm_unreachable("Invalid builtin type.");
@@ -4110,6 +4116,9 @@
#define PPC_VECTOR_TYPE(Name, Id, Size) \
case BuiltinType::Id:
#include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) \
+ case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
case BuiltinType::BuiltinFn:
case BuiltinType::NullPtr:
case BuiltinType::IncompleteMatrixIdx:
Index: clang/lib/AST/PrintfFormatString.cpp
===================================================================
--- clang/lib/AST/PrintfFormatString.cpp
+++ clang/lib/AST/PrintfFormatString.cpp
@@ -794,6 +794,9 @@
#define PPC_VECTOR_TYPE(Name, Id, Size) \
case BuiltinType::Id:
#include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) \
+ case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
#define SIGNED_TYPE(Id, SingletonId)
#define UNSIGNED_TYPE(Id, SingletonId)
#define FLOATING_TYPE(Id, SingletonId)
Index: clang/lib/AST/NSAPI.cpp
===================================================================
--- clang/lib/AST/NSAPI.cpp
+++ clang/lib/AST/NSAPI.cpp
@@ -477,6 +477,9 @@
#define PPC_VECTOR_TYPE(Name, Id, Size) \
case BuiltinType::Id:
#include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) \
+ case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
case BuiltinType::BoundMember:
case BuiltinType::Dependent:
case BuiltinType::Overload:
Index: clang/lib/AST/MicrosoftMangle.cpp
===================================================================
--- clang/lib/AST/MicrosoftMangle.cpp
+++ clang/lib/AST/MicrosoftMangle.cpp
@@ -2398,6 +2398,9 @@
#define PPC_VECTOR_TYPE(Name, Id, Size) \
case BuiltinType::Id:
#include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) \
+ case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
case BuiltinType::ShortAccum:
case BuiltinType::Accum:
case BuiltinType::LongAccum:
Index: clang/lib/AST/ItaniumMangle.cpp
===================================================================
--- clang/lib/AST/ItaniumMangle.cpp
+++ clang/lib/AST/ItaniumMangle.cpp
@@ -2864,6 +2864,13 @@
Out << 'u' << type_name.size() << type_name; \
break;
#include "clang/Basic/PPCTypes.def"
+ // TODO: Check the mangling scheme for RISC-V V.
+#define RVV_TYPE(Name, Id, SingletonId) \
+ case BuiltinType::Id: \
+ type_name = Name; \
+ Out << 'u' << type_name.size() << type_name; \
+ break;
+#include "clang/Basic/RISCVVTypes.def"
}
}
Index: clang/lib/AST/ExprConstant.cpp
===================================================================
--- clang/lib/AST/ExprConstant.cpp
+++ clang/lib/AST/ExprConstant.cpp
@@ -10971,6 +10971,9 @@
#define PPC_VECTOR_TYPE(Name, Id, Size) \
case BuiltinType::Id:
#include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) \
+ case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
return GCCTypeClass::None;
case BuiltinType::Dependent:
Index: clang/lib/AST/ASTImporter.cpp
===================================================================
--- clang/lib/AST/ASTImporter.cpp
+++ clang/lib/AST/ASTImporter.cpp
@@ -1036,6 +1036,10 @@
case BuiltinType::Id: \
return Importer.getToContext().Id##Ty;
#include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) \
+ case BuiltinType::Id: \
+ return Importer.getToContext().SingletonId;
+#include "clang/Basic/RISCVVTypes.def"
#define SHARED_SINGLETON_TYPE(Expansion)
#define BUILTIN_TYPE(Id, SingletonId) \
case BuiltinType::Id: return Importer.getToContext().SingletonId;
Index: clang/lib/AST/ASTContext.cpp
===================================================================
--- clang/lib/AST/ASTContext.cpp
+++ clang/lib/AST/ASTContext.cpp
@@ -1435,6 +1435,12 @@
#include "clang/Basic/PPCTypes.def"
}
+ if (Target.hasRISCVVTypes()) {
+#define RVV_TYPE(Name, Id, SingletonId) \
+ InitBuiltinType(SingletonId, BuiltinType::Id);
+#include "clang/Basic/RISCVVTypes.def"
+ }
+
// Builtin type for __objc_yes and __objc_no
ObjCBuiltinBoolTy = (Target.useSignedCharForObjCBool() ?
SignedCharTy : BoolTy);
@@ -2166,6 +2172,18 @@
Align = Size; \
break;
#include "clang/Basic/PPCTypes.def"
+#define RVV_VECTOR_TYPE(Name, Id, SingletonId, ElKind, ElBits, NF, IsSigned, \
+ IsFP) \
+ case BuiltinType::Id: \
+ Width = 0; \
+ Align = 128; \
+ break;
+#define RVV_PREDICATE_TYPE(Name, Id, SingletonId, ElKind) \
+ case BuiltinType::Id: \
+ Width = 0; \
+ Align = 64; \
+ break;
+#include "clang/Basic/RISCVVTypes.def"
}
break;
case Type::ObjCObjectPointer:
@@ -3810,6 +3828,20 @@
return SVE_ELTTY(BFloat16Ty, 8, 3);
case BuiltinType::SveBFloat16x4:
return SVE_ELTTY(BFloat16Ty, 8, 4);
+#define RVV_VECTOR_TYPE_INT(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned) \
+ case BuiltinType::Id: \
+ return {getIntTypeForBitwidth(ElBits, IsSigned), \
+ llvm::ElementCount::getScalable(NumEls), \
+ NF};
+#define RVV_VECTOR_TYPE_FLOAT(Name, Id, SingletonId, NumEls, ElBits, NF) \
+ case BuiltinType::Id: \
+ return {ElBits == 16 ? HalfTy : (ElBits == 32 ? FloatTy : DoubleTy), \
+ llvm::ElementCount::getScalable(NumEls), \
+ NF};
+#define RVV_PREDICATE_TYPE(Name, Id, SingletonId, NumEls) \
+ case BuiltinType::Id: \
+ return {BoolTy, llvm::ElementCount::getScalable(NumEls), 1};
+#include "clang/Basic/RISCVVTypes.def"
}
}
@@ -3836,6 +3868,20 @@
if (EltTy->isBooleanType() && NumElts == NumEls) \
return SingletonId;
#include "clang/Basic/AArch64SVEACLETypes.def"
+ } else if (Target->hasRISCVVTypes()) {
+ uint64_t EltTySize = getTypeSize(EltTy);
+#define RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned, \
+ IsFP) \
+ if (!EltTy->isBooleanType() && \
+ ((EltTy->hasIntegerRepresentation() && \
+ EltTy->hasSignedIntegerRepresentation() == IsSigned) || \
+ (EltTy->hasFloatingRepresentation() && IsFP)) && \
+ EltTySize == ElBits && NumElts == NumEls) \
+ return SingletonId;
+#define RVV_PREDICATE_TYPE(Name, Id, SingletonId, NumEls) \
+ if (EltTy->isBooleanType() && NumElts == NumEls) \
+ return SingletonId;
+#include "clang/Basic/RISCVVTypes.def"
}
return QualType();
}
@@ -7212,6 +7258,9 @@
#define SVE_TYPE(Name, Id, SingletonId) \
case BuiltinType::Id:
#include "clang/Basic/AArch64SVEACLETypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) \
+ case BuiltinType::Id:
+#include "clang/Basic/RISCVVTypes.def"
{
DiagnosticsEngine &Diags = C->getDiagnostics();
unsigned DiagID = Diags.getCustomDiagID(
Index: clang/include/clang/module.modulemap
===================================================================
--- clang/include/clang/module.modulemap
+++ clang/include/clang/module.modulemap
@@ -63,6 +63,7 @@
textual header "Basic/OpenMPKinds.def"
textual header "Basic/OperatorKinds.def"
textual header "Basic/PPCTypes.def"
+ textual header "Basic/RISCVVTypes.def"
textual header "Basic/Sanitizers.def"
textual header "Basic/TokenKinds.def"
textual header "Basic/X86Target.def"
Index: clang/include/clang/Serialization/ASTBitCodes.h
===================================================================
--- clang/include/clang/Serialization/ASTBitCodes.h
+++ clang/include/clang/Serialization/ASTBitCodes.h
@@ -1083,6 +1083,9 @@
// \brief PowerPC MMA types with auto numeration
#define PPC_VECTOR_TYPE(Name, Id, Size) PREDEF_TYPE_##Id##_ID,
#include "clang/Basic/PPCTypes.def"
+ // \brief RISC-V V types with auto numeration
+#define RVV_TYPE(Name, Id, SingletonId) PREDEF_TYPE_##Id##_ID,
+#include "clang/Basic/RISCVVTypes.def"
};
/// The number of predefined type IDs that are reserved for
@@ -1090,7 +1093,7 @@
///
/// Type IDs for non-predefined types will start at
/// NUM_PREDEF_TYPE_IDs.
- const unsigned NUM_PREDEF_TYPE_IDS = 200;
+ const unsigned NUM_PREDEF_TYPE_IDS = 300;
/// Record codes for each kind of type.
///
Index: clang/include/clang/Basic/TargetInfo.h
===================================================================
--- clang/include/clang/Basic/TargetInfo.h
+++ clang/include/clang/Basic/TargetInfo.h
@@ -218,6 +218,8 @@
unsigned HasAArch64SVETypes : 1;
+ unsigned HasRISCVVTypes : 1;
+
unsigned AllowAMDGPUUnsafeFPAtomics : 1;
unsigned ARMCDECoprocMask : 8;
@@ -859,6 +861,10 @@
/// available on this target.
bool hasAArch64SVETypes() const { return HasAArch64SVETypes; }
+ /// Returns whether or not the RISC-V V built-in types are
+ /// available on this target.
+ bool hasRISCVVTypes() const { return HasRISCVVTypes; }
+
/// Returns whether or not the AMDGPU unsafe floating point atomics are
/// allowed.
bool allowAMDGPUUnsafeFPAtomics() const { return AllowAMDGPUUnsafeFPAtomics; }
Index: clang/include/clang/Basic/RISCVVTypes.def
===================================================================
--- /dev/null
+++ clang/include/clang/Basic/RISCVVTypes.def
@@ -0,0 +1,147 @@
+//===-- RISCVVTypes.def - Metadata for the RISC-V V types ------*- C++ -*--===//
+//
+// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
+// See https://llvm.org/LICENSE.txt for license information.
+// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
+//
+//===----------------------------------------------------------------------===//
+//
+// This file defines various RISC-V V builtin types. The macros are:
+//
+// - RVV_TYPE(Name, Id, SingletonId)
+// A builtin type that has not been covered by any other #define
+// Defining this macro covers all the builtins.
+//
+// - RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, IsSigned, IsFP)
+// A RISC-V V scalable vector.
+//
+// - RVV_PREDICATE_TYPE(Name, Id, SingletonId, NumEls)
+// An RISC-V V scalable mask.
+//
+// where:
+//
+// - Name is the name of the builtin type.
+//
+// - Id is the enumerator defining the type.
+//
+// - SingletonId is the global singleton of this type.
+//
+// - NumEls enumerates the number of the elements.
+//
+// - ElBits is the size of one element in bits (SEW).
+//
+// - NF is the number of fields (NFIELDS) used in the Zvlsseg instructions
+// (TODO).
+//
+// - IsSigned is true for vectors of signed integer elements and
+// for vectors of floating-point elements.
+//
+// - IsFP is true for vectors of floating-point elements.
+//
+//===----------------------------------------------------------------------===//
+
+#ifndef RVV_VECTOR_TYPE
+#define RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned, IsFP)\
+ RVV_TYPE(Name, Id, SingletonId)
+#endif
+
+#ifndef RVV_PREDICATE_TYPE
+#define RVV_PREDICATE_TYPE(Name, Id, SingletonId, NumEls)\
+ RVV_TYPE(Name, Id, SingletonId)
+#endif
+
+#ifndef RVV_VECTOR_TYPE_INT
+#define RVV_VECTOR_TYPE_INT(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned) \
+ RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, IsSigned, false)
+#endif
+
+#ifndef RVV_VECTOR_TYPE_FLOAT
+#define RVV_VECTOR_TYPE_FLOAT(Name, Id, SingletonId, NumEls, ElBits, NF) \
+ RVV_VECTOR_TYPE(Name, Id, SingletonId, NumEls, ElBits, NF, false, true)
+#endif
+
+//===- Vector types -------------------------------------------------------===//
+
+RVV_VECTOR_TYPE_INT("__rvv_int8mf8_t", RvvInt8mf8, RvvInt8mf8Ty, 1, 8, 1, true)
+RVV_VECTOR_TYPE_INT("__rvv_int8mf4_t", RvvInt8mf4, RvvInt8mf4Ty, 2, 8, 1, true)
+RVV_VECTOR_TYPE_INT("__rvv_int8mf2_t", RvvInt8mf2, RvvInt8mf2Ty, 4, 8, 1, true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m1_t", RvvInt8m1, RvvInt8m1Ty, 8, 8, 1, true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m2_t", RvvInt8m2, RvvInt8m2Ty, 16, 8, 1, true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m4_t", RvvInt8m4, RvvInt8m4Ty, 32, 8, 1, true)
+RVV_VECTOR_TYPE_INT("__rvv_int8m8_t", RvvInt8m8, RvvInt8m8Ty, 64, 8, 1, true)
+
+RVV_VECTOR_TYPE_INT("__rvv_uint8mf8_t",RvvUint8mf8,RvvUint8mf8Ty,1, 8, 1, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint8mf4_t",RvvUint8mf4,RvvUint8mf4Ty,2, 8, 1, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint8mf2_t",RvvUint8mf2,RvvUint8mf2Ty,4, 8, 1, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint8m1_t", RvvUint8m1, RvvUint8m1Ty, 8, 8, 1, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint8m2_t", RvvUint8m2, RvvUint8m2Ty, 16, 8, 1, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint8m4_t", RvvUint8m4, RvvUint8m4Ty, 32, 8, 1, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint8m8_t", RvvUint8m8, RvvUint8m8Ty, 64, 8, 1, false)
+
+RVV_VECTOR_TYPE_INT("__rvv_int16mf4_t",RvvInt16mf4,RvvInt16mf4Ty,1, 16, 1, true)
+RVV_VECTOR_TYPE_INT("__rvv_int16mf2_t",RvvInt16mf2,RvvInt16mf2Ty,2, 16, 1, true)
+RVV_VECTOR_TYPE_INT("__rvv_int16m1_t", RvvInt16m1, RvvInt16m1Ty, 4, 16, 1, true)
+RVV_VECTOR_TYPE_INT("__rvv_int16m2_t", RvvInt16m2, RvvInt16m2Ty, 8, 16, 1, true)
+RVV_VECTOR_TYPE_INT("__rvv_int16m4_t", RvvInt16m4, RvvInt16m4Ty, 16, 16, 1, true)
+RVV_VECTOR_TYPE_INT("__rvv_int16m8_t", RvvInt16m8, RvvInt16m8Ty, 32, 16, 1, true)
+
+RVV_VECTOR_TYPE_INT("__rvv_uint16mf4_t",RvvUint16mf4,RvvUint16mf4Ty,1, 16, 1, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint16mf2_t",RvvUint16mf2,RvvUint16mf2Ty,2, 16, 1, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint16m1_t", RvvUint16m1, RvvUint16m1Ty, 4, 16, 1, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint16m2_t", RvvUint16m2, RvvUint16m2Ty, 8, 16, 1, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint16m4_t", RvvUint16m4, RvvUint16m4Ty, 16, 16, 1, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint16m8_t", RvvUint16m8, RvvUint16m8Ty, 32, 16, 1, false)
+
+RVV_VECTOR_TYPE_INT("__rvv_int32mf2_t",RvvInt32mf2,RvvInt32mf2Ty,1, 32, 1, true)
+RVV_VECTOR_TYPE_INT("__rvv_int32m1_t", RvvInt32m1, RvvInt32m1Ty, 2, 32, 1, true)
+RVV_VECTOR_TYPE_INT("__rvv_int32m2_t", RvvInt32m2, RvvInt32m2Ty, 4, 32, 1, true)
+RVV_VECTOR_TYPE_INT("__rvv_int32m4_t", RvvInt32m4, RvvInt32m4Ty, 8, 32, 1, true)
+RVV_VECTOR_TYPE_INT("__rvv_int32m8_t", RvvInt32m8, RvvInt32m8Ty, 16, 32, 1, true)
+
+RVV_VECTOR_TYPE_INT("__rvv_uint32mf2_t",RvvUint32mf2,RvvUint32mf2Ty,1, 32, 1, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint32m1_t", RvvUint32m1, RvvUint32m1Ty, 2, 32, 1, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint32m2_t", RvvUint32m2, RvvUint32m2Ty, 4, 32, 1, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint32m4_t", RvvUint32m4, RvvUint32m4Ty, 8, 32, 1, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint32m8_t", RvvUint32m8, RvvUint32m8Ty, 16, 32, 1, false)
+
+RVV_VECTOR_TYPE_INT("__rvv_int64m1_t", RvvInt64m1, RvvInt64m1Ty, 1, 64, 1, true)
+RVV_VECTOR_TYPE_INT("__rvv_int64m2_t", RvvInt64m2, RvvInt64m2Ty, 2, 64, 1, true)
+RVV_VECTOR_TYPE_INT("__rvv_int64m4_t", RvvInt64m4, RvvInt64m4Ty, 4, 64, 1, true)
+RVV_VECTOR_TYPE_INT("__rvv_int64m8_t", RvvInt64m8, RvvInt64m8Ty, 8, 64, 1, true)
+
+RVV_VECTOR_TYPE_INT("__rvv_uint64m1_t",RvvUint64m1,RvvUint64m1Ty,1, 64, 1, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint64m2_t",RvvUint64m2,RvvUint64m2Ty,2, 64, 1, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint64m4_t",RvvUint64m4,RvvUint64m4Ty,4, 64, 1, false)
+RVV_VECTOR_TYPE_INT("__rvv_uint64m8_t",RvvUint64m8,RvvUint64m8Ty,8, 64, 1, false)
+
+RVV_VECTOR_TYPE_FLOAT("__rvv_float16mf4_t",RvvFloat16mf4,RvvFloat16mf4Ty,1, 16, 1)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float16mf2_t",RvvFloat16mf2,RvvFloat16mf2Ty,2, 16, 1)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float16m1_t", RvvFloat16m1, RvvFloat16m1Ty, 4, 16, 1)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float16m2_t", RvvFloat16m2, RvvFloat16m2Ty, 8, 16, 1)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float16m4_t", RvvFloat16m4, RvvFloat16m4Ty, 16, 16, 1)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float16m8_t", RvvFloat16m8, RvvFloat16m8Ty, 32, 16, 1)
+
+RVV_VECTOR_TYPE_FLOAT("__rvv_float32mf2_t",RvvFloat32mf2,RvvFloat32mf2Ty,1, 32, 1)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float32m1_t", RvvFloat32m1, RvvFloat32m1Ty, 2, 32, 1)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float32m2_t", RvvFloat32m2, RvvFloat32m2Ty, 4, 32, 1)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float32m4_t", RvvFloat32m4, RvvFloat32m4Ty, 8, 32, 1)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float32m8_t", RvvFloat32m8, RvvFloat32m8Ty, 16, 32, 1)
+
+RVV_VECTOR_TYPE_FLOAT("__rvv_float64m1_t", RvvFloat64m1, RvvFloat64m1Ty, 1, 64, 1)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float64m2_t", RvvFloat64m2, RvvFloat64m2Ty, 2, 64, 1)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float64m4_t", RvvFloat64m4, RvvFloat64m4Ty, 4, 64, 1)
+RVV_VECTOR_TYPE_FLOAT("__rvv_float64m8_t", RvvFloat64m8, RvvFloat64m8Ty, 8, 64, 1)
+
+RVV_PREDICATE_TYPE("__rvv_bool1_t", RvvBool1, RvvBool1Ty, 64)
+RVV_PREDICATE_TYPE("__rvv_bool2_t", RvvBool2, RvvBool2Ty, 32)
+RVV_PREDICATE_TYPE("__rvv_bool4_t", RvvBool4, RvvBool4Ty, 16)
+RVV_PREDICATE_TYPE("__rvv_bool8_t", RvvBool8, RvvBool8Ty, 8)
+RVV_PREDICATE_TYPE("__rvv_bool16_t", RvvBool16, RvvBool16Ty, 4)
+RVV_PREDICATE_TYPE("__rvv_bool32_t", RvvBool32, RvvBool32Ty, 2)
+RVV_PREDICATE_TYPE("__rvv_bool64_t", RvvBool64, RvvBool64Ty, 1)
+
+#undef RVV_VECTOR_TYPE_FLOAT
+#undef RVV_VECTOR_TYPE_INT
+#undef RVV_VECTOR_TYPE
+#undef RVV_PREDICATE_TYPE
+#undef RVV_TYPE
Index: clang/include/clang/AST/TypeProperties.td
===================================================================
--- clang/include/clang/AST/TypeProperties.td
+++ clang/include/clang/AST/TypeProperties.td
@@ -769,6 +769,10 @@
case BuiltinType::ID: return ctx.ID##Ty;
#include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(NAME, ID, SINGLETON_ID) \
+ case BuiltinType::ID: return ctx.SINGLETON_ID;
+#include "clang/Basic/RISCVVTypes.def"
+
#define BUILTIN_TYPE(ID, SINGLETON_ID) \
case BuiltinType::ID: return ctx.SINGLETON_ID;
#include "clang/AST/BuiltinTypes.def"
Index: clang/include/clang/AST/Type.h
===================================================================
--- clang/include/clang/AST/Type.h
+++ clang/include/clang/AST/Type.h
@@ -2491,6 +2491,9 @@
// PPC MMA Types
#define PPC_VECTOR_TYPE(Name, Id, Size) Id,
#include "clang/Basic/PPCTypes.def"
+// RVV Types
+#define RVV_TYPE(Name, Id, SingletonId) Id,
+#include "clang/Basic/RISCVVTypes.def"
// All other builtin types
#define BUILTIN_TYPE(Id, SingletonId) Id,
#define LAST_BUILTIN_TYPE(Id) LastKind = Id
Index: clang/include/clang/AST/ASTContext.h
===================================================================
--- clang/include/clang/AST/ASTContext.h
+++ clang/include/clang/AST/ASTContext.h
@@ -1010,6 +1010,9 @@
#define PPC_VECTOR_TYPE(Name, Id, Size) \
CanQualType Id##Ty;
#include "clang/Basic/PPCTypes.def"
+#define RVV_TYPE(Name, Id, SingletonId) \
+ CanQualType SingletonId;
+#include "clang/Basic/RISCVVTypes.def"
// Types for deductions in C++0x [stmt.ranged]'s desugaring. Built on demand.
mutable QualType AutoDeductTy; // Deduction against 'auto'.
_______________________________________________
cfe-commits mailing list
cfe-commits@lists.llvm.org
https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
