[PATCH] D94779: [Clang] Ensure vector predication pragma is ignored only when vectorization width is 1.

[Sjoerd Meijer via Phabricator via cfe-commits]

SjoerdMeijer added inline comments.


================
Comment at: clang/test/CodeGenCXX/pragma-loop-predicate.cpp:102
+
+// CHECK-NEXT: ![[LOOP7]] = distinct !{![[LOOP7]], [[MP]], [[GEN8]], 
[[GEN11:![0-9]+]], [[GEN3]]}
+// CHECK-NEXT: [[GEN11]] = !{!"llvm.loop.vectorize.width", i32 4}
----------------
Do we also expect:

   !{!"llvm.loop.vectorize.predicate.enable", i1 false}

here since the test sets:

  vectorize_predicate(disable) vectorize_width(4)


Repository:
  rG LLVM Github Monorepo

CHANGES SINCE LAST ACTION
  https://reviews.llvm.org/D94779/new/

https://reviews.llvm.org/D94779

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