MaskRay created this revision.
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brucehoult, MartinMosbeck, rogfer01, edward-jones, zzheng, jrtc27, shiva0217,
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kristof.beyls.
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Herald added projects: clang, LLVM.
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Similar to D72215 <https://reviews.llvm.org/D72215> (AArch64) and D72220
<https://reviews.llvm.org/D72220> (x86).
Recently the mainline kernel started to use -fpatchable-function-entry=8 for
riscv (https://git.kernel.org/linus/afc76b8b80112189b6f11e67e19cf58301944814).
Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D98610
Files:
clang/include/clang/Basic/Attr.td
clang/lib/Driver/ToolChains/Clang.cpp
clang/test/Driver/fpatchable-function-entry.c
clang/test/Sema/patchable-function-entry-attr.cpp
llvm/lib/Target/RISCV/RISCV.h
llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.h
llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
llvm/test/CodeGen/RISCV/patchable-function-entry.ll
Index: llvm/test/CodeGen/RISCV/patchable-function-entry.ll
===================================================================
--- /dev/null
+++ llvm/test/CodeGen/RISCV/patchable-function-entry.ll
@@ -0,0 +1,72 @@
+;; Test the function attribute "patchable-function-entry".
+; RUN: llc -mtriple=riscv32 < %s | FileCheck %s --check-prefixes=CHECK,32
+; RUN: llc -mtriple=riscv64 < %s | FileCheck %s --check-prefixes=CHECK,64
+
+; RUN: llc -filetype=obj -mtriple=riscv64 %s -o %t.o
+; RUN: llvm-objdump -d %t.o | FileCheck %s --check-prefix=NORVC
+; RUN: llc -filetype=obj -mtriple=riscv64 -mattr=+c %s -o %tc.o
+; RUN: llvm-objdump -d %tc.o | FileCheck %s --check-prefix=RVC
+
+; NORVC: 13 00 00 00 nop
+; RVC: 01 00 nop
+
+define void @f0() "patchable-function-entry"="0" {
+; CHECK-LABEL: f0:
+; CHECK-NEXT: .Lfunc_begin0:
+; CHECK-NOT: nop
+; CHECK: ret
+; CHECK-NOT: .section __patchable_function_entries
+ ret void
+}
+
+define void @f1() "patchable-function-entry"="1" {
+; CHECK-LABEL: f1:
+; CHECK-NEXT: .Lfunc_begin1:
+; CHECK: nop
+; CHECK-NEXT: ret
+; CHECK: .section __patchable_function_entries,"awo",@progbits,f1{{$}}
+; 32: .p2align 2
+; 32-NEXT: .word .Lfunc_begin1
+; 64: .p2align 3
+; 64-NEXT: .quad .Lfunc_begin1
+ ret void
+}
+
+$f5 = comdat any
+define void @f5() "patchable-function-entry"="5" comdat {
+; CHECK-LABEL: f5:
+; CHECK-NEXT: .Lfunc_begin2:
+; CHECK-COUNT-5: nop
+; CHECK-NEXT: ret
+; CHECK: .section __patchable_function_entries,"aGwo",@progbits,f5,comdat,f5{{$}}
+; 32: .p2align 2
+; 32-NEXT: .word .Lfunc_begin2
+; 64: .p2align 3
+; 64-NEXT: .quad .Lfunc_begin2
+ ret void
+}
+
+;; -fpatchable-function-entry=3,2
+;; "patchable-function-prefix" emits data before the function entry label.
+;; We emit 1-byte NOPs before the function entry, so that with a partial patch,
+;; the remaining instructions do not need to be modified.
+define void @f3_2() "patchable-function-entry"="1" "patchable-function-prefix"="2" {
+; CHECK-LABEL: .type f3_2,@function
+; CHECK-NEXT: .Ltmp0: # @f3_2
+; CHECK-NEXT: nop
+; CHECK-NEXT: nop
+; CHECK-NEXT: f3_2:
+; CHECK: # %bb.0:
+; CHECK-NEXT: nop
+; CHECK-NEXT: addi sp, sp, -16
+;; .size does not include the prefix.
+; CHECK: .Lfunc_end3:
+; CHECK-NEXT: .size f3_2, .Lfunc_end3-f3_2
+; CHECK: .section __patchable_function_entries,"awo",@progbits,f3_2{{$}}
+; 32: .p2align 2
+; 32-NEXT: .word .Ltmp0
+; 64: .p2align 3
+; 64-NEXT: .quad .Ltmp0
+ %frame = alloca i8, i32 16
+ ret void
+}
Index: llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
+++ llvm/lib/Target/RISCV/RISCVMCInstLower.cpp
@@ -204,10 +204,10 @@
return true;
}
-void llvm::LowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
- const AsmPrinter &AP) {
+bool llvm::lowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
+ AsmPrinter &AP) {
if (lowerRISCVVMachineInstrToMCInst(MI, OutMI))
- return;
+ return false;
OutMI.setOpcode(MI->getOpcode());
@@ -217,19 +217,32 @@
OutMI.addOperand(MCOp);
}
- if (OutMI.getOpcode() == RISCV::PseudoReadVLENB) {
+ switch (OutMI.getOpcode()) {
+ case TargetOpcode::PATCHABLE_FUNCTION_ENTER: {
+ const Function &F = MI->getParent()->getParent()->getFunction();
+ if (F.hasFnAttribute("patchable-function-entry")) {
+ unsigned Num;
+ if (F.getFnAttribute("patchable-function-entry")
+ .getValueAsString()
+ .getAsInteger(10, Num))
+ return false;
+ AP.emitNops(Num);
+ return true;
+ }
+ break;
+ }
+ case RISCV::PseudoReadVLENB:
OutMI.setOpcode(RISCV::CSRRS);
OutMI.addOperand(MCOperand::createImm(
RISCVSysReg::lookupSysRegByName("VLENB")->Encoding));
OutMI.addOperand(MCOperand::createReg(RISCV::X0));
- return;
- }
-
- if (OutMI.getOpcode() == RISCV::PseudoReadVL) {
+ break;
+ case RISCV::PseudoReadVL:
OutMI.setOpcode(RISCV::CSRRS);
- OutMI.addOperand(MCOperand::createImm(
- RISCVSysReg::lookupSysRegByName("VL")->Encoding));
+ OutMI.addOperand(
+ MCOperand::createImm(RISCVSysReg::lookupSysRegByName("VL")->Encoding));
OutMI.addOperand(MCOperand::createReg(RISCV::X0));
- return;
+ break;
}
+ return false;
}
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.h
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.h
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.h
@@ -29,6 +29,8 @@
public:
explicit RISCVInstrInfo(RISCVSubtarget &STI);
+ void getNoop(MCInst &NopInst) const override;
+
unsigned isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const override;
unsigned isStoreToStackSlot(const MachineInstr &MI,
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.cpp
@@ -23,6 +23,7 @@
#include "llvm/CodeGen/MachineInstrBuilder.h"
#include "llvm/CodeGen/MachineRegisterInfo.h"
#include "llvm/CodeGen/RegisterScavenging.h"
+#include "llvm/MC/MCInstBuilder.h"
#include "llvm/Support/ErrorHandling.h"
#include "llvm/Support/TargetRegistry.h"
@@ -49,6 +50,16 @@
: RISCVGenInstrInfo(RISCV::ADJCALLSTACKDOWN, RISCV::ADJCALLSTACKUP),
STI(STI) {}
+void RISCVInstrInfo::getNoop(MCInst &NopInst) const {
+ if (STI.getFeatureBits()[RISCV::FeatureStdExtC])
+ NopInst = MCInstBuilder(RISCV::C_NOP);
+ else
+ NopInst = MCInstBuilder(RISCV::ADDI)
+ .addReg(RISCV::X0)
+ .addReg(RISCV::X0)
+ .addImm(0);
+}
+
unsigned RISCVInstrInfo::isLoadFromStackSlot(const MachineInstr &MI,
int &FrameIndex) const {
switch (MI.getOpcode()) {
Index: llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
+++ llvm/lib/Target/RISCV/RISCVAsmPrinter.cpp
@@ -93,8 +93,8 @@
return;
MCInst TmpInst;
- LowerRISCVMachineInstrToMCInst(MI, TmpInst, *this);
- EmitToStreamer(*OutStreamer, TmpInst);
+ if (!lowerRISCVMachineInstrToMCInst(MI, TmpInst, *this))
+ EmitToStreamer(*OutStreamer, TmpInst);
}
bool RISCVAsmPrinter::PrintAsmOperand(const MachineInstr *MI, unsigned OpNo,
Index: llvm/lib/Target/RISCV/RISCV.h
===================================================================
--- llvm/lib/Target/RISCV/RISCV.h
+++ llvm/lib/Target/RISCV/RISCV.h
@@ -30,8 +30,8 @@
class MachineOperand;
class PassRegistry;
-void LowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
- const AsmPrinter &AP);
+bool lowerRISCVMachineInstrToMCInst(const MachineInstr *MI, MCInst &OutMI,
+ AsmPrinter &AP);
bool LowerRISCVMachineOperandToMCOperand(const MachineOperand &MO,
MCOperand &MCOp, const AsmPrinter &AP);
Index: clang/test/Sema/patchable-function-entry-attr.cpp
===================================================================
--- clang/test/Sema/patchable-function-entry-attr.cpp
+++ clang/test/Sema/patchable-function-entry-attr.cpp
@@ -2,6 +2,8 @@
// RUN: %clang_cc1 -triple aarch64_be -fsyntax-only -verify=silence %s
// RUN: %clang_cc1 -triple i386 -fsyntax-only -verify=silence %s
// RUN: %clang_cc1 -triple x86_64 -fsyntax-only -verify=silence %s
+// RUN: %clang_cc1 -triple riscv32 -fsyntax-only -verify=silence %s
+// RUN: %clang_cc1 -triple riscv64 -fsyntax-only -verify=silence %s
// RUN: %clang_cc1 -triple ppc64le -fsyntax-only -verify %s
// silence-no-diagnostics
Index: clang/test/Driver/fpatchable-function-entry.c
===================================================================
--- clang/test/Driver/fpatchable-function-entry.c
+++ clang/test/Driver/fpatchable-function-entry.c
@@ -2,6 +2,8 @@
// RUN: %clang -target x86_64 %s -fpatchable-function-entry=1 -c -### 2>&1 | FileCheck %s
// RUN: %clang -target aarch64 %s -fpatchable-function-entry=1 -c -### 2>&1 | FileCheck %s
// RUN: %clang -target aarch64 %s -fpatchable-function-entry=1,0 -c -### 2>&1 | FileCheck %s
+// RUN: %clang -target riscv32 %s -fpatchable-function-entry=1,0 -c -### 2>&1 | FileCheck %s
+// RUN: %clang -target riscv64 %s -fpatchable-function-entry=1,0 -c -### 2>&1 | FileCheck %s
// CHECK: "-fpatchable-function-entry=1"
// RUN: %clang -target aarch64 -fsyntax-only %s -fpatchable-function-entry=1,1 -c -### 2>&1 | FileCheck --check-prefix=11 %s
Index: clang/lib/Driver/ToolChains/Clang.cpp
===================================================================
--- clang/lib/Driver/ToolChains/Clang.cpp
+++ clang/lib/Driver/ToolChains/Clang.cpp
@@ -5614,8 +5614,7 @@
if (Arg *A = Args.getLastArg(options::OPT_fpatchable_function_entry_EQ)) {
StringRef S0 = A->getValue(), S = S0;
unsigned Size, Offset = 0;
- if (!Triple.isAArch64() && Triple.getArch() != llvm::Triple::x86 &&
- Triple.getArch() != llvm::Triple::x86_64)
+ if (!Triple.isAArch64() && !Triple.isRISCV() && !Triple.isX86())
D.Diag(diag::err_drv_unsupported_opt_for_target)
<< A->getAsString(Args) << TripleStr;
else if (S.consumeInteger(10, Size) ||
Index: clang/include/clang/Basic/Attr.td
===================================================================
--- clang/include/clang/Basic/Attr.td
+++ clang/include/clang/Basic/Attr.td
@@ -730,7 +730,8 @@
def PatchableFunctionEntry
: InheritableAttr,
- TargetSpecificAttr<TargetArch<["aarch64", "aarch64_be", "x86", "x86_64"]>> {
+ TargetSpecificAttr<TargetArch<
+ ["aarch64", "aarch64_be", "riscv32", "riscv64", "x86", "x86_64"]>> {
let Spellings = [GCC<"patchable_function_entry">];
let Subjects = SubjectList<[Function, ObjCMethod]>;
let Args = [UnsignedArgument<"Count">, DefaultIntArgument<"Offset", 0>];
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