frasercrmck added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCVISelLowering.cpp:715-732
+ if (Subtarget.is64Bit()) {
+ addTypeForP(MVT::v8i8, MVT::i64);
+ addTypeForP(MVT::v4i16, MVT::i64);
+ addTypeForP(MVT::v2i32, MVT::i64);
+ } else {
+ addTypeForP(MVT::v4i8, MVT::i32);
+ addTypeForP(MVT::v2i16, MVT::i32);
----------------
jrtc27 wrote:
> This seems like it will interact poorly with V if both are present
Indeed. I don't think we've really thought about how both of these could
co-exist in llvm. I'm not sure they can. We don't have the context to decide
upon how to lower an operation (to V or P) since we're just given the type.
Do we have to error if both are enabled simultaneously? Maybe if P only expects
to be lowered via intrinsics we can fudge it. It's not pretty though. I came
across this issue in a previous architecture where we had a v2i32 (or
something) able to be lowered both via "scalar" and "vector" instructions.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D99158/new/
https://reviews.llvm.org/D99158
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