DavidSpickett added a comment. What's your logic for these being Arm only?
I looked up the ones that were added: vadd_p8 vadd_p16 vadd_p64 vaddq_p8 vaddq_p16 vaddq_p64 vaddq_p128 E.g. https://developer.arm.com/architectures/instruction-sets/simd-isas/neon/intrinsics?search=vadd_p8 It says that this is enabled for `v7/A32/A64`. However the pseudocode does use `CheckFPAdvSIMDEnabled64` which might imply AArch64 only. There is a `AArch32.CheckAdvSIMDOrFPEnabled` for AArch32 but looking at `vabdq_u32` which is Arm and AArch64, it also uses `CheckFPAdvSIMDEnabled64` so clearly that doesn't mean much. The weird thing is that the header already guards this with `__aarch64__` so that must be based on some other property than simply being in these tables. (GCC agrees) How did you find this? Presumably you couldn't use them from C, even without this patch. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D100499/new/ https://reviews.llvm.org/D100499 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
