Jim added a comment. In D99158#2695125 <https://reviews.llvm.org/D99158#2695125>, @craig.topper wrote:
> Also can you please explain the vector codegen plan at a high level? Do you > intend to support auto vectorization or just using vector_size in C? Currently, it just supports vector type operation (like v4i8+v4i8=>add8) in my local patch. ================ Comment at: llvm/test/CodeGen/RISCV/rvp/intrinsics-rv32p.ll:25 + %1 = bitcast i32 %b.coerce to <4 x i8> + %2 = tail call <4 x i8> @llvm.riscv.add8.v4i8(<4 x i8> %0, <4 x i8> %1) + %3 = bitcast <4 x i8> %2 to i32 ---------------- craig.topper wrote: > I'm still not clear why we need to have two different ways to do the same > operation. Why isn't the C interface all scalar types or all vector types? > How do users choose which interface to use? I will ask P extension intrinsic designer about your concern. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D99158/new/ https://reviews.llvm.org/D99158 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
