Author: Hsiangkai Wang Date: 2021-04-26T15:38:31+08:00 New Revision: 4b2434172cc15ccd32c5c9110a3a4df18b8fba5e
URL: https://github.com/llvm/llvm-project/commit/4b2434172cc15ccd32c5c9110a3a4df18b8fba5e DIFF: https://github.com/llvm/llvm-project/commit/4b2434172cc15ccd32c5c9110a3a4df18b8fba5e.diff LOG: [RISCV] Implement the vmmv.m/vmnot.m builtin. Differential Revision: https://reviews.llvm.org/D100821 Added: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmmv.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmnot.c clang/test/CodeGen/RISCV/rvv-intrinsics/vmmv.c clang/test/CodeGen/RISCV/rvv-intrinsics/vmnot.c Modified: clang/include/clang/Basic/riscv_vector.td Removed: ################################################################################ diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td index d56a130aad16..d94ec15159ba 100644 --- a/clang/include/clang/Basic/riscv_vector.td +++ b/clang/include/clang/Basic/riscv_vector.td @@ -844,6 +844,23 @@ multiclass RVVPseudoVNotBuiltin<string IR, string type_range> { } } +multiclass RVVPseudoMaskBuiltin<string IR, string type_range> { + let Name = NAME, + IRName = IR, + HasMask = false, + ManualCodegen = [{ + { + // op1, vl + IntrinsicTypes = {ResultType, + Ops[1]->getType()}; + Ops.insert(Ops.begin() + 1, Ops[0]); + break; + } + }] in { + def : RVVBuiltin<"m", "mm", type_range>; + } +} + // 6. Configuration-Setting Instructions // 6.1. vsetvli/vsetvl instructions let HasVL = false, @@ -1300,6 +1317,8 @@ def vmxnor : RVVMaskBinBuiltin; // pseudoinstructions def vmclr : RVVMaskNullaryBuiltin; def vmset : RVVMaskNullaryBuiltin; +defm vmmv_m : RVVPseudoMaskBuiltin<"vmand", "c">; +defm vmnot_m : RVVPseudoMaskBuiltin<"vmnand", "c">; // 16.2. Vector mask population count vpopc def vpopc : RVVMaskOp0Builtin<"um">; diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmmv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmmv.c new file mode 100644 index 000000000000..ee2b6412d59b --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmmv.c @@ -0,0 +1,105 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include <riscv_vector.h> + +// CHECK-RV32-LABEL: @test_vmmv_m_b1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i32(<vscale x 64 x i1> [[OP1:%.*]], <vscale x 64 x i1> [[OP1]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 64 x i1> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmmv_m_b1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.*]], <vscale x 64 x i1> [[OP1]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]] +// +vbool1_t test_vmmv_m_b1 (vbool1_t op1, size_t vl) { + return vmmv(op1, vl); +} + +// CHECK-RV32-LABEL: @test_vmmv_m_b2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i32(<vscale x 32 x i1> [[OP1:%.*]], <vscale x 32 x i1> [[OP1]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 32 x i1> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmmv_m_b2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1> [[OP1:%.*]], <vscale x 32 x i1> [[OP1]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]] +// +vbool2_t test_vmmv_m_b2 (vbool2_t op1, size_t vl) { + return vmmv(op1, vl); +} + +// CHECK-RV32-LABEL: @test_vmmv_m_b4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i32(<vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[OP1]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 16 x i1> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmmv_m_b4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[OP1]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]] +// +vbool4_t test_vmmv_m_b4 (vbool4_t op1, size_t vl) { + return vmmv(op1, vl); +} + +// CHECK-RV32-LABEL: @test_vmmv_m_b8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i32(<vscale x 8 x i1> [[OP1:%.*]], <vscale x 8 x i1> [[OP1]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 8 x i1> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmmv_m_b8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1> [[OP1:%.*]], <vscale x 8 x i1> [[OP1]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]] +// +vbool8_t test_vmmv_m_b8 (vbool8_t op1, size_t vl) { + return vmmv(op1, vl); +} + +// CHECK-RV32-LABEL: @test_vmmv_m_b16( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i32(<vscale x 4 x i1> [[OP1:%.*]], <vscale x 4 x i1> [[OP1]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 4 x i1> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmmv_m_b16( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1> [[OP1:%.*]], <vscale x 4 x i1> [[OP1]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]] +// +vbool16_t test_vmmv_m_b16 (vbool16_t op1, size_t vl) { + return vmmv(op1, vl); +} + +// CHECK-RV32-LABEL: @test_vmmv_m_b32( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i32(<vscale x 2 x i1> [[OP1:%.*]], <vscale x 2 x i1> [[OP1]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 2 x i1> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmmv_m_b32( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1> [[OP1:%.*]], <vscale x 2 x i1> [[OP1]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]] +// +vbool32_t test_vmmv_m_b32 (vbool32_t op1, size_t vl) { + return vmmv(op1, vl); +} + +// CHECK-RV32-LABEL: @test_vmmv_m_b64( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i32(<vscale x 1 x i1> [[OP1:%.*]], <vscale x 1 x i1> [[OP1]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 1 x i1> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmmv_m_b64( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1> [[OP1:%.*]], <vscale x 1 x i1> [[OP1]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]] +// +vbool64_t test_vmmv_m_b64 (vbool64_t op1, size_t vl) { + return vmmv(op1, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmnot.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmnot.c new file mode 100644 index 000000000000..5f07a238f04d --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vmnot.c @@ -0,0 +1,105 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// REQUIRES: riscv-registered-target +// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s + +#include <riscv_vector.h> + +// CHECK-RV32-LABEL: @test_vmnot_m_b1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i32(<vscale x 64 x i1> [[OP1:%.*]], <vscale x 64 x i1> [[OP1]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 64 x i1> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmnot_m_b1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.*]], <vscale x 64 x i1> [[OP1]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]] +// +vbool1_t test_vmnot_m_b1 (vbool1_t op1, size_t vl) { + return vmnot(op1, vl); +} + +// CHECK-RV32-LABEL: @test_vmnot_m_b2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i32(<vscale x 32 x i1> [[OP1:%.*]], <vscale x 32 x i1> [[OP1]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 32 x i1> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmnot_m_b2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1> [[OP1:%.*]], <vscale x 32 x i1> [[OP1]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]] +// +vbool2_t test_vmnot_m_b2 (vbool2_t op1, size_t vl) { + return vmnot(op1, vl); +} + +// CHECK-RV32-LABEL: @test_vmnot_m_b4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i32(<vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[OP1]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 16 x i1> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmnot_m_b4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[OP1]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]] +// +vbool4_t test_vmnot_m_b4 (vbool4_t op1, size_t vl) { + return vmnot(op1, vl); +} + +// CHECK-RV32-LABEL: @test_vmnot_m_b8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i32(<vscale x 8 x i1> [[OP1:%.*]], <vscale x 8 x i1> [[OP1]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 8 x i1> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmnot_m_b8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1> [[OP1:%.*]], <vscale x 8 x i1> [[OP1]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]] +// +vbool8_t test_vmnot_m_b8 (vbool8_t op1, size_t vl) { + return vmnot(op1, vl); +} + +// CHECK-RV32-LABEL: @test_vmnot_m_b16( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i32(<vscale x 4 x i1> [[OP1:%.*]], <vscale x 4 x i1> [[OP1]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 4 x i1> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmnot_m_b16( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1> [[OP1:%.*]], <vscale x 4 x i1> [[OP1]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]] +// +vbool16_t test_vmnot_m_b16 (vbool16_t op1, size_t vl) { + return vmnot(op1, vl); +} + +// CHECK-RV32-LABEL: @test_vmnot_m_b32( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i32(<vscale x 2 x i1> [[OP1:%.*]], <vscale x 2 x i1> [[OP1]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 2 x i1> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmnot_m_b32( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1> [[OP1:%.*]], <vscale x 2 x i1> [[OP1]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]] +// +vbool32_t test_vmnot_m_b32 (vbool32_t op1, size_t vl) { + return vmnot(op1, vl); +} + +// CHECK-RV32-LABEL: @test_vmnot_m_b64( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i32(<vscale x 1 x i1> [[OP1:%.*]], <vscale x 1 x i1> [[OP1]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 1 x i1> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmnot_m_b64( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1> [[OP1:%.*]], <vscale x 1 x i1> [[OP1]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]] +// +vbool64_t test_vmnot_m_b64 (vbool64_t op1, size_t vl) { + return vmnot(op1, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmmv.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmmv.c new file mode 100644 index 000000000000..adb3a142447f --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmmv.c @@ -0,0 +1,107 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -target-feature +m -Werror -Wall -S -o - %s >/dev/null 2>%t +// RUN: FileCheck --check-prefix=ASM --allow-empty %s <%t + +// ASM-NOT: warning +#include <riscv_vector.h> + +// CHECK-RV32-LABEL: @test_vmmv_m_b1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i32(<vscale x 64 x i1> [[OP1:%.*]], <vscale x 64 x i1> [[OP1]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 64 x i1> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmmv_m_b1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmand.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.*]], <vscale x 64 x i1> [[OP1]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]] +// +vbool1_t test_vmmv_m_b1 (vbool1_t op1, size_t vl) { + return vmmv_m_b1(op1, vl); +} + +// CHECK-RV32-LABEL: @test_vmmv_m_b2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i32(<vscale x 32 x i1> [[OP1:%.*]], <vscale x 32 x i1> [[OP1]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 32 x i1> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmmv_m_b2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmand.nxv32i1.i64(<vscale x 32 x i1> [[OP1:%.*]], <vscale x 32 x i1> [[OP1]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]] +// +vbool2_t test_vmmv_m_b2 (vbool2_t op1, size_t vl) { + return vmmv_m_b2(op1, vl); +} + +// CHECK-RV32-LABEL: @test_vmmv_m_b4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i32(<vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[OP1]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 16 x i1> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmmv_m_b4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmand.nxv16i1.i64(<vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[OP1]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]] +// +vbool4_t test_vmmv_m_b4 (vbool4_t op1, size_t vl) { + return vmmv_m_b4(op1, vl); +} + +// CHECK-RV32-LABEL: @test_vmmv_m_b8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i32(<vscale x 8 x i1> [[OP1:%.*]], <vscale x 8 x i1> [[OP1]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 8 x i1> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmmv_m_b8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmand.nxv8i1.i64(<vscale x 8 x i1> [[OP1:%.*]], <vscale x 8 x i1> [[OP1]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]] +// +vbool8_t test_vmmv_m_b8 (vbool8_t op1, size_t vl) { + return vmmv_m_b8(op1, vl); +} + +// CHECK-RV32-LABEL: @test_vmmv_m_b16( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i32(<vscale x 4 x i1> [[OP1:%.*]], <vscale x 4 x i1> [[OP1]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 4 x i1> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmmv_m_b16( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmand.nxv4i1.i64(<vscale x 4 x i1> [[OP1:%.*]], <vscale x 4 x i1> [[OP1]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]] +// +vbool16_t test_vmmv_m_b16 (vbool16_t op1, size_t vl) { + return vmmv_m_b16(op1, vl); +} + +// CHECK-RV32-LABEL: @test_vmmv_m_b32( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i32(<vscale x 2 x i1> [[OP1:%.*]], <vscale x 2 x i1> [[OP1]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 2 x i1> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmmv_m_b32( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmand.nxv2i1.i64(<vscale x 2 x i1> [[OP1:%.*]], <vscale x 2 x i1> [[OP1]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]] +// +vbool32_t test_vmmv_m_b32 (vbool32_t op1, size_t vl) { + return vmmv_m_b32(op1, vl); +} + +// CHECK-RV32-LABEL: @test_vmmv_m_b64( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i32(<vscale x 1 x i1> [[OP1:%.*]], <vscale x 1 x i1> [[OP1]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 1 x i1> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmmv_m_b64( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmand.nxv1i1.i64(<vscale x 1 x i1> [[OP1:%.*]], <vscale x 1 x i1> [[OP1]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]] +// +vbool64_t test_vmmv_m_b64 (vbool64_t op1, size_t vl) { + return vmmv_m_b64(op1, vl); +} + diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vmnot.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmnot.c new file mode 100644 index 000000000000..a79d7dce4bbd --- /dev/null +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vmnot.c @@ -0,0 +1,107 @@ +// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py +// RUN: %clang_cc1 -triple riscv32 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV32 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s +// RUN: %clang_cc1 -triple riscv64 -target-feature +experimental-v -target-feature +m -Werror -Wall -S -o - %s >/dev/null 2>%t +// RUN: FileCheck --check-prefix=ASM --allow-empty %s <%t + +// ASM-NOT: warning +#include <riscv_vector.h> + +// CHECK-RV32-LABEL: @test_vmnot_m_b1( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i32(<vscale x 64 x i1> [[OP1:%.*]], <vscale x 64 x i1> [[OP1]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 64 x i1> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmnot_m_b1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 64 x i1> @llvm.riscv.vmnand.nxv64i1.i64(<vscale x 64 x i1> [[OP1:%.*]], <vscale x 64 x i1> [[OP1]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 64 x i1> [[TMP0]] +// +vbool1_t test_vmnot_m_b1 (vbool1_t op1, size_t vl) { + return vmnot_m_b1(op1, vl); +} + +// CHECK-RV32-LABEL: @test_vmnot_m_b2( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i32(<vscale x 32 x i1> [[OP1:%.*]], <vscale x 32 x i1> [[OP1]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 32 x i1> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmnot_m_b2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x i1> @llvm.riscv.vmnand.nxv32i1.i64(<vscale x 32 x i1> [[OP1:%.*]], <vscale x 32 x i1> [[OP1]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 32 x i1> [[TMP0]] +// +vbool2_t test_vmnot_m_b2 (vbool2_t op1, size_t vl) { + return vmnot_m_b2(op1, vl); +} + +// CHECK-RV32-LABEL: @test_vmnot_m_b4( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i32(<vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[OP1]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 16 x i1> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmnot_m_b4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x i1> @llvm.riscv.vmnand.nxv16i1.i64(<vscale x 16 x i1> [[OP1:%.*]], <vscale x 16 x i1> [[OP1]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 16 x i1> [[TMP0]] +// +vbool4_t test_vmnot_m_b4 (vbool4_t op1, size_t vl) { + return vmnot_m_b4(op1, vl); +} + +// CHECK-RV32-LABEL: @test_vmnot_m_b8( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i32(<vscale x 8 x i1> [[OP1:%.*]], <vscale x 8 x i1> [[OP1]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 8 x i1> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmnot_m_b8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x i1> @llvm.riscv.vmnand.nxv8i1.i64(<vscale x 8 x i1> [[OP1:%.*]], <vscale x 8 x i1> [[OP1]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 8 x i1> [[TMP0]] +// +vbool8_t test_vmnot_m_b8 (vbool8_t op1, size_t vl) { + return vmnot_m_b8(op1, vl); +} + +// CHECK-RV32-LABEL: @test_vmnot_m_b16( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i32(<vscale x 4 x i1> [[OP1:%.*]], <vscale x 4 x i1> [[OP1]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 4 x i1> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmnot_m_b16( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x i1> @llvm.riscv.vmnand.nxv4i1.i64(<vscale x 4 x i1> [[OP1:%.*]], <vscale x 4 x i1> [[OP1]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 4 x i1> [[TMP0]] +// +vbool16_t test_vmnot_m_b16 (vbool16_t op1, size_t vl) { + return vmnot_m_b16(op1, vl); +} + +// CHECK-RV32-LABEL: @test_vmnot_m_b32( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i32(<vscale x 2 x i1> [[OP1:%.*]], <vscale x 2 x i1> [[OP1]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 2 x i1> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmnot_m_b32( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x i1> @llvm.riscv.vmnand.nxv2i1.i64(<vscale x 2 x i1> [[OP1:%.*]], <vscale x 2 x i1> [[OP1]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x i1> [[TMP0]] +// +vbool32_t test_vmnot_m_b32 (vbool32_t op1, size_t vl) { + return vmnot_m_b32(op1, vl); +} + +// CHECK-RV32-LABEL: @test_vmnot_m_b64( +// CHECK-RV32-NEXT: entry: +// CHECK-RV32-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i32(<vscale x 1 x i1> [[OP1:%.*]], <vscale x 1 x i1> [[OP1]], i32 [[VL:%.*]]) +// CHECK-RV32-NEXT: ret <vscale x 1 x i1> [[TMP0]] +// +// CHECK-RV64-LABEL: @test_vmnot_m_b64( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x i1> @llvm.riscv.vmnand.nxv1i1.i64(<vscale x 1 x i1> [[OP1:%.*]], <vscale x 1 x i1> [[OP1]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 1 x i1> [[TMP0]] +// +vbool64_t test_vmnot_m_b64 (vbool64_t op1, size_t vl) { + return vmnot_m_b64(op1, vl); +} + _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits