dmgreen added a comment.
Sounds good.
================
Comment at: llvm/lib/Target/AArch64/AArch64InstrInfo.td:4134
-defm RBIT : SIMDTwoVectorB<1, 0b01, 0b00101, "rbit", int_aarch64_neon_rbit>;
+//defm RBIT : SIMDTwoVectorB<1, 0b01, 0b00101, "rbit",
int_aarch64_neon_rbit>;
+defm RBIT : SIMDTwoVectorB<1, 0b01, 0b00101, "rbit", bitreverse>;
----------------
We can remove this. And Can we remove the definition on int_aarch64_neon_rbit
now too?
================
Comment at: llvm/test/CodeGen/AArch64/bitreverse.ll:33
define <8 x i8> @g_vec(<8 x i8> %a) {
+;CHECK-LABEL: g_vec:
----------------
Can we add tests for all these types:
v8i8 v16i8
v4i16 v8i16
v2i32 v4i32
v1i64 v2i64
Then use update_llc_test_checks to generate the check lines. Also i32 and i64
would be good to have in here.
Bonus points for pre-committing with the old codegen, to just show changes here.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D102397/new/
https://reviews.llvm.org/D102397
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