Author: Hsiangkai Wang Date: 2021-08-09T17:38:15+08:00 New Revision: 5f996705e0cadc43771da12dec0670680230ca56
URL: https://github.com/llvm/llvm-project/commit/5f996705e0cadc43771da12dec0670680230ca56 DIFF: https://github.com/llvm/llvm-project/commit/5f996705e0cadc43771da12dec0670680230ca56.diff LOG: [RISCV] Half-precision for vget/vset. Differential Revision: https://reviews.llvm.org/D107433 Added: Modified: clang/include/clang/Basic/riscv_vector.td clang/test/CodeGen/RISCV/rvv-intrinsics/vget.c clang/test/CodeGen/RISCV/rvv-intrinsics/vset.c Removed: ################################################################################ diff --git a/clang/include/clang/Basic/riscv_vector.td b/clang/include/clang/Basic/riscv_vector.td index 48c032dd1422b..ebe32860882a4 100644 --- a/clang/include/clang/Basic/riscv_vector.td +++ b/clang/include/clang/Basic/riscv_vector.td @@ -2086,7 +2086,7 @@ let HasMask = false, HasVL = false, IRName = "" in { } }] in { foreach dst_lmul = ["(SFixedLog2LMUL:0)", "(SFixedLog2LMUL:1)", "(SFixedLog2LMUL:2)"] in { - def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "vvKz", "csilfd", dst_lmul # "v">; + def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "vvKz", "csilxfd", dst_lmul # "v">; def : RVVBuiltin<"Uv" # dst_lmul # "Uv", dst_lmul # "UvUvKz", "csil", dst_lmul # "Uv">; } } @@ -2105,7 +2105,7 @@ let HasMask = false, HasVL = false, IRName = "" in { } }] in { foreach dst_lmul = ["(LFixedLog2LMUL:1)", "(LFixedLog2LMUL:2)", "(LFixedLog2LMUL:3)"] in { - def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "v" # dst_lmul # "vKzv", "csilfd">; + def : RVVBuiltin<"v" # dst_lmul # "v", dst_lmul # "v" # dst_lmul # "vKzv", "csilxfd">; def : RVVBuiltin<"Uv" # dst_lmul # "Uv", dst_lmul # "Uv" # dst_lmul #"UvKzUv", "csil">; } } diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vget.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vget.c index ac287ff294019..4526d1891bcfb 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vget.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vget.c @@ -1,6 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ +// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include <riscv_vector.h> @@ -544,3 +545,57 @@ vfloat64m2_t test_vget_v_f64m8_f64m2(vfloat64m8_t src) { vfloat64m4_t test_vget_v_f64m8_f64m4(vfloat64m8_t src) { return vget_v_f64m8_f64m4(src, 1); } + +// CHECK-RV64-LABEL: @test_vget_v_f16m2_f16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.experimental.vector.extract.nxv4f16.nxv8f16(<vscale x 8 x half> [[SRC:%.*]], i64 0) +// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] +// +vfloat16m1_t test_vget_v_f16m2_f16m1 (vfloat16m2_t src) { + return vget_v_f16m2_f16m1(src, 0); +} + +// CHECK-RV64-LABEL: @test_vget_v_f16m4_f16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.experimental.vector.extract.nxv4f16.nxv16f16(<vscale x 16 x half> [[SRC:%.*]], i64 0) +// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] +// +vfloat16m1_t test_vget_v_f16m4_f16m1 (vfloat16m4_t src) { + return vget_v_f16m4_f16m1(src, 0); +} + +// CHECK-RV64-LABEL: @test_vget_v_f16m8_f16m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 4 x half> @llvm.experimental.vector.extract.nxv4f16.nxv32f16(<vscale x 32 x half> [[SRC:%.*]], i64 0) +// CHECK-RV64-NEXT: ret <vscale x 4 x half> [[TMP0]] +// +vfloat16m1_t test_vget_v_f16m8_f16m1 (vfloat16m8_t src) { + return vget_v_f16m8_f16m1(src, 0); +} + +// CHECK-RV64-LABEL: @test_vget_v_f16m4_f16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.experimental.vector.extract.nxv8f16.nxv16f16(<vscale x 16 x half> [[SRC:%.*]], i64 0) +// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] +// +vfloat16m2_t test_vget_v_f16m4_f16m2 (vfloat16m4_t src) { + return vget_v_f16m4_f16m2(src, 0); +} + +// CHECK-RV64-LABEL: @test_vget_v_f16m8_f16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.experimental.vector.extract.nxv8f16.nxv32f16(<vscale x 32 x half> [[SRC:%.*]], i64 0) +// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] +// +vfloat16m2_t test_vget_v_f16m8_f16m2 (vfloat16m8_t src) { + return vget_v_f16m8_f16m2(src, 0); +} + +// CHECK-RV64-LABEL: @test_vget_v_f16m8_f16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.experimental.vector.extract.nxv16f16.nxv32f16(<vscale x 32 x half> [[SRC:%.*]], i64 0) +// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] +// +vfloat16m4_t test_vget_v_f16m8_f16m4 (vfloat16m8_t src) { + return vget_v_f16m8_f16m4(src, 0); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vset.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vset.c index 95da8010aeb26..0bd0cf08c433c 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vset.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vset.c @@ -1,6 +1,7 @@ // NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py // REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d -target-feature +experimental-v \ +// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ +// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ // RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s #include <riscv_vector.h> @@ -544,3 +545,57 @@ vfloat64m8_t test_vset_v_f64m2_f64m8(vfloat64m8_t dest, vfloat64m2_t val) { vfloat64m8_t test_vset_v_f64m4_f64m8(vfloat64m8_t dest, vfloat64m4_t val) { return vset_v_f64m4_f64m8(dest, 1, val); } + +// CHECK-RV64-LABEL: @test_vset_v_f16m1_f16m2( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 8 x half> @llvm.experimental.vector.insert.nxv8f16.nxv4f16(<vscale x 8 x half> [[DEST:%.*]], <vscale x 4 x half> [[VAL:%.*]], i64 0) +// CHECK-RV64-NEXT: ret <vscale x 8 x half> [[TMP0]] +// +vfloat16m2_t test_vset_v_f16m1_f16m2 (vfloat16m2_t dest, vfloat16m1_t val) { + return vset_v_f16m1_f16m2(dest, 0, val); +} + +// CHECK-RV64-LABEL: @test_vset_v_f16m1_f16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.experimental.vector.insert.nxv16f16.nxv4f16(<vscale x 16 x half> [[DEST:%.*]], <vscale x 4 x half> [[VAL:%.*]], i64 0) +// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] +// +vfloat16m4_t test_vset_v_f16m1_f16m4 (vfloat16m4_t dest, vfloat16m1_t val) { + return vset_v_f16m1_f16m4(dest, 0, val); +} + +// CHECK-RV64-LABEL: @test_vset_v_f16m2_f16m4( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 16 x half> @llvm.experimental.vector.insert.nxv16f16.nxv8f16(<vscale x 16 x half> [[DEST:%.*]], <vscale x 8 x half> [[VAL:%.*]], i64 0) +// CHECK-RV64-NEXT: ret <vscale x 16 x half> [[TMP0]] +// +vfloat16m4_t test_vset_v_f16m2_f16m4 (vfloat16m4_t dest, vfloat16m2_t val) { + return vset_v_f16m2_f16m4(dest, 0, val); +} + +// CHECK-RV64-LABEL: @test_vset_v_f16m1_f16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.experimental.vector.insert.nxv32f16.nxv4f16(<vscale x 32 x half> [[DEST:%.*]], <vscale x 4 x half> [[VAL:%.*]], i64 0) +// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] +// +vfloat16m8_t test_vset_v_f16m1_f16m8 (vfloat16m8_t dest, vfloat16m1_t val) { + return vset_v_f16m1_f16m8(dest, 0, val); +} + +// CHECK-RV64-LABEL: @test_vset_v_f16m2_f16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.experimental.vector.insert.nxv32f16.nxv8f16(<vscale x 32 x half> [[DEST:%.*]], <vscale x 8 x half> [[VAL:%.*]], i64 0) +// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] +// +vfloat16m8_t test_vset_v_f16m2_f16m8 (vfloat16m8_t dest, vfloat16m2_t val) { + return vset_v_f16m2_f16m8(dest, 0, val); +} + +// CHECK-RV64-LABEL: @test_vset_v_f16m4_f16m8( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 32 x half> @llvm.experimental.vector.insert.nxv32f16.nxv16f16(<vscale x 32 x half> [[DEST:%.*]], <vscale x 16 x half> [[VAL:%.*]], i64 0) +// CHECK-RV64-NEXT: ret <vscale x 32 x half> [[TMP0]] +// +vfloat16m8_t test_vset_v_f16m4_f16m8 (vfloat16m8_t dest, vfloat16m4_t val) { + return vset_v_f16m4_f16m8(dest, 0, val); +} _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits