zixuan-wu added inline comments.
================ Comment at: llvm/lib/Target/RISCV/MCTargetDesc/RISCVBaseInfo.cpp:107 + for (auto Feature : RISCVFeatureKV) { + if (FeatureBits[Feature.Value] && + llvm::RISCVISAInfo::isSupportedExtensionFeature(Feature.Key)) ---------------- If SubtargetFeature is enum value like ARM.td does, Feature.Value would be a uninitialization value, so I think there should be if condition like `Feature.Value < RISCV::NumSubtargetFeatures`, or there is a out-of-range visit. ``` def ProcXXX : SubtargetFeature<"", "RISCVProcFamily", "XXX", "XXX processors">; ``` Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D105168/new/ https://reviews.llvm.org/D105168 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits