Author: Craig Topper Date: 2021-11-02T10:33:20-07:00 New Revision: 98b761fce68b194674a98f347c641f8ce3e85eff
URL: https://github.com/llvm/llvm-project/commit/98b761fce68b194674a98f347c641f8ce3e85eff DIFF: https://github.com/llvm/llvm-project/commit/98b761fce68b194674a98f347c641f8ce3e85eff.diff LOG: [RISCV] Rename vfredusum/vfredosum intrinsic test files. Merge some tests. NFC I recently renamed some tests from vfredsum to vfredusum without noticing they tested both ordered and unordered reductions. This patch renames them back. I've also merged test files for vfwredosum/vfwredusum into a single file for consistency with the other 3 floating point reduction test files. The inconsistency is what caused my original confusion. Added: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredsum.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredsum.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfredsum.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredsum.c Modified: Removed: clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredusum.c clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredusum.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfredusum.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredosum.c clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredusum.c ################################################################################ diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredusum.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredsum.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredusum.c rename to clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfredsum.c diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredusum.c b/clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredsum.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredusum.c rename to clang/test/CodeGen/RISCV/rvv-intrinsics-overloaded/vfwredsum.c diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfredusum.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfredsum.c similarity index 100% rename from clang/test/CodeGen/RISCV/rvv-intrinsics/vfredusum.c rename to clang/test/CodeGen/RISCV/rvv-intrinsics/vfredsum.c diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredosum.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredsum.c similarity index 50% rename from clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredosum.c rename to clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredsum.c index 590cd741d155d..7c060e1829445 100644 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredosum.c +++ b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredsum.c @@ -223,3 +223,221 @@ vfloat32m1_t test_vfwredosum_vs_f16m4_f32m1_m (vbool4_t mask, vfloat32m1_t dest, vfloat32m1_t test_vfwredosum_vs_f16m8_f32m1_m (vbool2_t mask, vfloat32m1_t dest, vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) { return vfwredosum_vs_f16m8_f32m1_m(mask, dest, vector, scalar, vl); } + +// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32mf2_f64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] +// +vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1(vfloat64m1_t dst, + vfloat32mf2_t vector, + vfloat64m1_t scalar, size_t vl) { + return vfwredusum_vs_f32mf2_f64m1(dst, vector, scalar, vl); +} + +// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m1_f64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] +// +vfloat64m1_t test_vfwredusum_vs_f32m1_f64m1(vfloat64m1_t dst, + vfloat32m1_t vector, + vfloat64m1_t scalar, size_t vl) { + return vfwredusum_vs_f32m1_f64m1(dst, vector, scalar, vl); +} + +// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m2_f64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] +// +vfloat64m1_t test_vfwredusum_vs_f32m2_f64m1(vfloat64m1_t dst, + vfloat32m2_t vector, + vfloat64m1_t scalar, size_t vl) { + return vfwredusum_vs_f32m2_f64m1(dst, vector, scalar, vl); +} + +// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m4_f64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv8f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] +// +vfloat64m1_t test_vfwredusum_vs_f32m4_f64m1(vfloat64m1_t dst, + vfloat32m4_t vector, + vfloat64m1_t scalar, size_t vl) { + return vfwredusum_vs_f32m4_f64m1(dst, vector, scalar, vl); +} + +// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m8_f64m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv16f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] +// +vfloat64m1_t test_vfwredusum_vs_f32m8_f64m1(vfloat64m1_t dst, + vfloat32m8_t vector, + vfloat64m1_t scalar, size_t vl) { + return vfwredusum_vs_f32m8_f64m1(dst, vector, scalar, vl); +} + +// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32mf2_f64m1_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] +// +vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1_m(vbool64_t mask, vfloat64m1_t dst, + vfloat32mf2_t vector, + vfloat64m1_t scalar, size_t vl) { + return vfwredusum_vs_f32mf2_f64m1_m(mask, dst, vector, scalar, vl); +} + +// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m1_f64m1_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv2f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] +// +vfloat64m1_t test_vfwredusum_vs_f32m1_f64m1_m(vbool32_t mask, vfloat64m1_t dst, + vfloat32m1_t vector, + vfloat64m1_t scalar, size_t vl) { + return vfwredusum_vs_f32m1_f64m1_m(mask, dst, vector, scalar, vl); +} + +// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m2_f64m1_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv4f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] +// +vfloat64m1_t test_vfwredusum_vs_f32m2_f64m1_m(vbool16_t mask, vfloat64m1_t dst, + vfloat32m2_t vector, + vfloat64m1_t scalar, size_t vl) { + return vfwredusum_vs_f32m2_f64m1_m(mask, dst, vector, scalar, vl); +} + +// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m4_f64m1_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv8f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] +// +vfloat64m1_t test_vfwredusum_vs_f32m4_f64m1_m(vbool8_t mask, vfloat64m1_t dst, + vfloat32m4_t vector, + vfloat64m1_t scalar, size_t vl) { + return vfwredusum_vs_f32m4_f64m1_m(mask, dst, vector, scalar, vl); +} + +// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m8_f64m1_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv16f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] +// +vfloat64m1_t test_vfwredusum_vs_f32m8_f64m1_m(vbool4_t mask, vfloat64m1_t dst, + vfloat32m8_t vector, + vfloat64m1_t scalar, size_t vl) { + return vfwredusum_vs_f32m8_f64m1_m(mask, dst, vector, scalar, vl); +} + +// CHECK-RV64-LABEL: @test_vfwredusum_vs_f16mf4_f32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] +// +vfloat32m1_t test_vfwredusum_vs_f16mf4_f32m1 (vfloat32m1_t dest, vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) { + return vfwredusum_vs_f16mf4_f32m1(dest, vector, scalar, vl); +} + +// CHECK-RV64-LABEL: @test_vfwredusum_vs_f16mf2_f32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] +// +vfloat32m1_t test_vfwredusum_vs_f16mf2_f32m1 (vfloat32m1_t dest, vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) { + return vfwredusum_vs_f16mf2_f32m1(dest, vector, scalar, vl); +} + +// CHECK-RV64-LABEL: @test_vfwredusum_vs_f16m1_f32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] +// +vfloat32m1_t test_vfwredusum_vs_f16m1_f32m1 (vfloat32m1_t dest, vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) { + return vfwredusum_vs_f16m1_f32m1(dest, vector, scalar, vl); +} + +// CHECK-RV64-LABEL: @test_vfwredusum_vs_f16m2_f32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] +// +vfloat32m1_t test_vfwredusum_vs_f16m2_f32m1 (vfloat32m1_t dest, vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) { + return vfwredusum_vs_f16m2_f32m1(dest, vector, scalar, vl); +} + +// CHECK-RV64-LABEL: @test_vfwredusum_vs_f16m4_f32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] +// +vfloat32m1_t test_vfwredusum_vs_f16m4_f32m1 (vfloat32m1_t dest, vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) { + return vfwredusum_vs_f16m4_f32m1(dest, vector, scalar, vl); +} + +// CHECK-RV64-LABEL: @test_vfwredusum_vs_f16m8_f32m1( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] +// +vfloat32m1_t test_vfwredusum_vs_f16m8_f32m1 (vfloat32m1_t dest, vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) { + return vfwredusum_vs_f16m8_f32m1(dest, vector, scalar, vl); +} + +// CHECK-RV64-LABEL: @test_vfwredusum_vs_f16mf4_f32m1_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv1f16.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] +// +vfloat32m1_t test_vfwredusum_vs_f16mf4_f32m1_m (vbool64_t mask, vfloat32m1_t dest, vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) { + return vfwredusum_vs_f16mf4_f32m1_m(mask, dest, vector, scalar, vl); +} + +// CHECK-RV64-LABEL: @test_vfwredusum_vs_f16mf2_f32m1_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] +// +vfloat32m1_t test_vfwredusum_vs_f16mf2_f32m1_m (vbool32_t mask, vfloat32m1_t dest, vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) { + return vfwredusum_vs_f16mf2_f32m1_m(mask, dest, vector, scalar, vl); +} + +// CHECK-RV64-LABEL: @test_vfwredusum_vs_f16m1_f32m1_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv4f16.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] +// +vfloat32m1_t test_vfwredusum_vs_f16m1_f32m1_m (vbool16_t mask, vfloat32m1_t dest, vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) { + return vfwredusum_vs_f16m1_f32m1_m(mask, dest, vector, scalar, vl); +} + +// CHECK-RV64-LABEL: @test_vfwredusum_vs_f16m2_f32m1_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv8f16.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] +// +vfloat32m1_t test_vfwredusum_vs_f16m2_f32m1_m (vbool8_t mask, vfloat32m1_t dest, vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) { + return vfwredusum_vs_f16m2_f32m1_m(mask, dest, vector, scalar, vl); +} + +// CHECK-RV64-LABEL: @test_vfwredusum_vs_f16m4_f32m1_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv16f16.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] +// +vfloat32m1_t test_vfwredusum_vs_f16m4_f32m1_m (vbool4_t mask, vfloat32m1_t dest, vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) { + return vfwredusum_vs_f16m4_f32m1_m(mask, dest, vector, scalar, vl); +} + +// CHECK-RV64-LABEL: @test_vfwredusum_vs_f16m8_f32m1_m( +// CHECK-RV64-NEXT: entry: +// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv32f16.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) +// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] +// +vfloat32m1_t test_vfwredusum_vs_f16m8_f32m1_m (vbool2_t mask, vfloat32m1_t dest, vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) { + return vfwredusum_vs_f16m8_f32m1_m(mask, dest, vector, scalar, vl); +} diff --git a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredusum.c b/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredusum.c deleted file mode 100644 index 74a71208fddb9..0000000000000 --- a/clang/test/CodeGen/RISCV/rvv-intrinsics/vfwredusum.c +++ /dev/null @@ -1,225 +0,0 @@ -// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py -// REQUIRES: riscv-registered-target -// RUN: %clang_cc1 -triple riscv64 -target-feature +f -target-feature +d \ -// RUN: -target-feature +experimental-v -target-feature +experimental-zfh \ -// RUN: -disable-O0-optnone -emit-llvm %s -o - | opt -S -mem2reg | FileCheck --check-prefix=CHECK-RV64 %s - -#include <riscv_vector.h> - -// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32mf2_f64m1( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] -// -vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1(vfloat64m1_t dst, - vfloat32mf2_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfwredusum_vs_f32mf2_f64m1(dst, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m1_f64m1( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv2f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] -// -vfloat64m1_t test_vfwredusum_vs_f32m1_f64m1(vfloat64m1_t dst, - vfloat32m1_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfwredusum_vs_f32m1_f64m1(dst, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m2_f64m1( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv4f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] -// -vfloat64m1_t test_vfwredusum_vs_f32m2_f64m1(vfloat64m1_t dst, - vfloat32m2_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfwredusum_vs_f32m2_f64m1(dst, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m4_f64m1( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv8f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] -// -vfloat64m1_t test_vfwredusum_vs_f32m4_f64m1(vfloat64m1_t dst, - vfloat32m4_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfwredusum_vs_f32m4_f64m1(dst, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m8_f64m1( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.nxv1f64.nxv16f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] -// -vfloat64m1_t test_vfwredusum_vs_f32m8_f64m1(vfloat64m1_t dst, - vfloat32m8_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfwredusum_vs_f32m8_f64m1(dst, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32mf2_f64m1_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv1f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 1 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] -// -vfloat64m1_t test_vfwredusum_vs_f32mf2_f64m1_m(vbool64_t mask, vfloat64m1_t dst, - vfloat32mf2_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfwredusum_vs_f32mf2_f64m1_m(mask, dst, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m1_f64m1_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv2f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 2 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] -// -vfloat64m1_t test_vfwredusum_vs_f32m1_f64m1_m(vbool32_t mask, vfloat64m1_t dst, - vfloat32m1_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfwredusum_vs_f32m1_f64m1_m(mask, dst, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m2_f64m1_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv4f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 4 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] -// -vfloat64m1_t test_vfwredusum_vs_f32m2_f64m1_m(vbool16_t mask, vfloat64m1_t dst, - vfloat32m2_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfwredusum_vs_f32m2_f64m1_m(mask, dst, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m4_f64m1_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv8f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 8 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] -// -vfloat64m1_t test_vfwredusum_vs_f32m4_f64m1_m(vbool8_t mask, vfloat64m1_t dst, - vfloat32m4_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfwredusum_vs_f32m4_f64m1_m(mask, dst, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredusum_vs_f32m8_f64m1_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 1 x double> @llvm.riscv.vfwredusum.mask.nxv1f64.nxv16f32.i64(<vscale x 1 x double> [[DST:%.*]], <vscale x 16 x float> [[VECTOR:%.*]], <vscale x 1 x double> [[SCALAR:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 1 x double> [[TMP0]] -// -vfloat64m1_t test_vfwredusum_vs_f32m8_f64m1_m(vbool4_t mask, vfloat64m1_t dst, - vfloat32m8_t vector, - vfloat64m1_t scalar, size_t vl) { - return vfwredusum_vs_f32m8_f64m1_m(mask, dst, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredusum_vs_f16mf4_f32m1( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv1f16.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] -// -vfloat32m1_t test_vfwredusum_vs_f16mf4_f32m1 (vfloat32m1_t dest, vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) { - return vfwredusum_vs_f16mf4_f32m1(dest, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredusum_vs_f16mf2_f32m1( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv2f16.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] -// -vfloat32m1_t test_vfwredusum_vs_f16mf2_f32m1 (vfloat32m1_t dest, vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) { - return vfwredusum_vs_f16mf2_f32m1(dest, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredusum_vs_f16m1_f32m1( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv4f16.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] -// -vfloat32m1_t test_vfwredusum_vs_f16m1_f32m1 (vfloat32m1_t dest, vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) { - return vfwredusum_vs_f16m1_f32m1(dest, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredusum_vs_f16m2_f32m1( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv8f16.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] -// -vfloat32m1_t test_vfwredusum_vs_f16m2_f32m1 (vfloat32m1_t dest, vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) { - return vfwredusum_vs_f16m2_f32m1(dest, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredusum_vs_f16m4_f32m1( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv16f16.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] -// -vfloat32m1_t test_vfwredusum_vs_f16m4_f32m1 (vfloat32m1_t dest, vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) { - return vfwredusum_vs_f16m4_f32m1(dest, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredusum_vs_f16m8_f32m1( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.nxv2f32.nxv32f16.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] -// -vfloat32m1_t test_vfwredusum_vs_f16m8_f32m1 (vfloat32m1_t dest, vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) { - return vfwredusum_vs_f16m8_f32m1(dest, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredusum_vs_f16mf4_f32m1_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv1f16.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 1 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], <vscale x 1 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] -// -vfloat32m1_t test_vfwredusum_vs_f16mf4_f32m1_m (vbool64_t mask, vfloat32m1_t dest, vfloat16mf4_t vector, vfloat32m1_t scalar, size_t vl) { - return vfwredusum_vs_f16mf4_f32m1_m(mask, dest, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredusum_vs_f16mf2_f32m1_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv2f16.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 2 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], <vscale x 2 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] -// -vfloat32m1_t test_vfwredusum_vs_f16mf2_f32m1_m (vbool32_t mask, vfloat32m1_t dest, vfloat16mf2_t vector, vfloat32m1_t scalar, size_t vl) { - return vfwredusum_vs_f16mf2_f32m1_m(mask, dest, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredusum_vs_f16m1_f32m1_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv4f16.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 4 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], <vscale x 4 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] -// -vfloat32m1_t test_vfwredusum_vs_f16m1_f32m1_m (vbool16_t mask, vfloat32m1_t dest, vfloat16m1_t vector, vfloat32m1_t scalar, size_t vl) { - return vfwredusum_vs_f16m1_f32m1_m(mask, dest, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredusum_vs_f16m2_f32m1_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv8f16.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 8 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], <vscale x 8 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] -// -vfloat32m1_t test_vfwredusum_vs_f16m2_f32m1_m (vbool8_t mask, vfloat32m1_t dest, vfloat16m2_t vector, vfloat32m1_t scalar, size_t vl) { - return vfwredusum_vs_f16m2_f32m1_m(mask, dest, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredusum_vs_f16m4_f32m1_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv16f16.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 16 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], <vscale x 16 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] -// -vfloat32m1_t test_vfwredusum_vs_f16m4_f32m1_m (vbool4_t mask, vfloat32m1_t dest, vfloat16m4_t vector, vfloat32m1_t scalar, size_t vl) { - return vfwredusum_vs_f16m4_f32m1_m(mask, dest, vector, scalar, vl); -} - -// CHECK-RV64-LABEL: @test_vfwredusum_vs_f16m8_f32m1_m( -// CHECK-RV64-NEXT: entry: -// CHECK-RV64-NEXT: [[TMP0:%.*]] = call <vscale x 2 x float> @llvm.riscv.vfwredusum.mask.nxv2f32.nxv32f16.i64(<vscale x 2 x float> [[DEST:%.*]], <vscale x 32 x half> [[VECTOR:%.*]], <vscale x 2 x float> [[SCALAR:%.*]], <vscale x 32 x i1> [[MASK:%.*]], i64 [[VL:%.*]]) -// CHECK-RV64-NEXT: ret <vscale x 2 x float> [[TMP0]] -// -vfloat32m1_t test_vfwredusum_vs_f16m8_f32m1_m (vbool2_t mask, vfloat32m1_t dest, vfloat16m8_t vector, vfloat32m1_t scalar, size_t vl) { - return vfwredusum_vs_f16m8_f32m1_m(mask, dest, vector, scalar, vl); -} _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
