StephenFan added inline comments.
================ Comment at: llvm/lib/Target/RISCV/RISCV.td:547 +def : ProcessorModel<"xiangshan-nanhu", NoSchedModel, [Feature64Bit, + FeatureStdExtM, + FeatureStdExtA, ---------------- The document says that `xiangshan-nanhu` cpu support `RV64IMAFDC_zba_zbb_zbc_zbs_zbkb_zbkc_zbkx_zknd_zkne_zknh_zksed_zksh_svinval` . And it seems that `svinval` extension is not supported by llvm. Repository: rG LLVM Github Monorepo CHANGES SINCE LAST ACTION https://reviews.llvm.org/D122556/new/ https://reviews.llvm.org/D122556 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
