Author: Martin Storsjö Date: 2022-06-08T11:32:17+03:00 New Revision: 20ca739701d7b2e2aa4028f1a7853f6d0fa0c412
URL: https://github.com/llvm/llvm-project/commit/20ca739701d7b2e2aa4028f1a7853f6d0fa0c412 DIFF: https://github.com/llvm/llvm-project/commit/20ca739701d7b2e2aa4028f1a7853f6d0fa0c412.diff LOG: [doc] Add release notes about SEH unwind information on ARM Differential Revision: https://reviews.llvm.org/D127150 Added: Modified: clang/docs/ReleaseNotes.rst llvm/docs/ReleaseNotes.rst Removed: ################################################################################ diff --git a/clang/docs/ReleaseNotes.rst b/clang/docs/ReleaseNotes.rst index 8c4f7f48850f..1e95d3cef51c 100644 --- a/clang/docs/ReleaseNotes.rst +++ b/clang/docs/ReleaseNotes.rst @@ -353,6 +353,11 @@ Windows Support JustMyCode feature. Note, you may need to manually add ``/JMC`` as additional compile options in the Visual Studio since it currently assumes clang-cl does not support ``/JMC``. +- Implemented generation of SEH unwind information on ARM. (C++ exception + handling in MSVC mode is still unimplemented though.) + +- Switched MinGW mode on ARM to use SEH instead of DWARF for unwind information. + AIX Support ----------- diff --git a/llvm/docs/ReleaseNotes.rst b/llvm/docs/ReleaseNotes.rst index e588128b2b92..d2813bb86973 100644 --- a/llvm/docs/ReleaseNotes.rst +++ b/llvm/docs/ReleaseNotes.rst @@ -102,6 +102,8 @@ Changes to the ARM Backend versions. * Added a pass to workaround Cortex-A57 Erratum 1742098 and Cortex-A72 Erratum 1655431. This is enabled by default when targeting either CPU. +* Implemented generation of Windows SEH unwind information. +* Switched the MinGW target to use SEH instead of DWARF for unwind information. Changes to the AVR Backend -------------------------- _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
