This revision was landed with ongoing or failed builds.
This revision was automatically updated to reflect the committed changes.
Closed by commit rG67480b360ca0: [clang-format] Handle Verilog blocks (authored
by sstwcw).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D128711/new/
https://reviews.llvm.org/D128711
Files:
clang/lib/Format/FormatToken.h
clang/lib/Format/TokenAnnotator.cpp
clang/lib/Format/UnwrappedLineParser.cpp
clang/unittests/Format/FormatTestVerilog.cpp
clang/unittests/Format/TokenAnnotatorTest.cpp
Index: clang/unittests/Format/TokenAnnotatorTest.cpp
===================================================================
--- clang/unittests/Format/TokenAnnotatorTest.cpp
+++ clang/unittests/Format/TokenAnnotatorTest.cpp
@@ -825,6 +825,12 @@
ASSERT_EQ(Tokens.size(), 7u) << Tokens;
EXPECT_TOKEN(Tokens[2], tok::tilde, TT_UnaryOperator);
EXPECT_TOKEN(Tokens[3], tok::pipe, TT_UnaryOperator);
+ // Test for block label colons.
+ Tokens = Annotate("begin : x\n"
+ "end : x");
+ ASSERT_EQ(Tokens.size(), 7u);
+ EXPECT_TOKEN(Tokens[1], tok::colon, TT_VerilogBlockLabelColon);
+ EXPECT_TOKEN(Tokens[4], tok::colon, TT_VerilogBlockLabelColon);
}
} // namespace
Index: clang/unittests/Format/FormatTestVerilog.cpp
===================================================================
--- clang/unittests/Format/FormatTestVerilog.cpp
+++ clang/unittests/Format/FormatTestVerilog.cpp
@@ -66,6 +66,56 @@
verifyFormat("x = 16'sd?;");
}
+TEST_F(FormatTestVerilog, Block) {
+ verifyFormat("begin\n"
+ " x = x;\n"
+ "end");
+ verifyFormat("begin : x\n"
+ " x = x;\n"
+ "end : x");
+ verifyFormat("begin\n"
+ " x = x;\n"
+ " x = x;\n"
+ "end");
+ verifyFormat("fork\n"
+ " x = x;\n"
+ "join");
+ verifyFormat("fork\n"
+ " x = x;\n"
+ "join_any");
+ verifyFormat("fork\n"
+ " x = x;\n"
+ "join_none");
+ verifyFormat("generate\n"
+ " x = x;\n"
+ "endgenerate");
+ verifyFormat("generate : x\n"
+ " x = x;\n"
+ "endgenerate : x");
+ // Nested blocks.
+ verifyFormat("begin\n"
+ " begin\n"
+ " end\n"
+ "end");
+ verifyFormat("begin : x\n"
+ " begin\n"
+ " end\n"
+ "end : x");
+ verifyFormat("begin : x\n"
+ " begin : x\n"
+ " end : x\n"
+ "end : x");
+ verifyFormat("begin\n"
+ " begin : x\n"
+ " end : x\n"
+ "end");
+ // Test that 'disable fork' and 'rand join' don't get mistaken as blocks.
+ verifyFormat("disable fork;\n"
+ "x = x;");
+ verifyFormat("rand join x x;\n"
+ "x = x;");
+}
+
TEST_F(FormatTestVerilog, Delay) {
// Delay by the default unit.
verifyFormat("#0;");
@@ -129,10 +179,6 @@
" x = x;\n"
" x = x;\n"
"end");
- verifyFormat("disable fork;\n"
- "x = x;");
- verifyFormat("rand join x x;\n"
- "x = x;");
verifyFormat("if (x) fork\n"
" x = x;\n"
"join");
Index: clang/lib/Format/UnwrappedLineParser.cpp
===================================================================
--- clang/lib/Format/UnwrappedLineParser.cpp
+++ clang/lib/Format/UnwrappedLineParser.cpp
@@ -1888,6 +1888,14 @@
return;
}
+ if (Style.isVerilog()) {
+ if (Keywords.isVerilogBegin(*FormatTok)) {
+ parseBlock();
+ addUnwrappedLine();
+ return;
+ }
+ }
+
if (FormatTok->is(Keywords.kw_interface)) {
if (parseStructLike())
return;
Index: clang/lib/Format/TokenAnnotator.cpp
===================================================================
--- clang/lib/Format/TokenAnnotator.cpp
+++ clang/lib/Format/TokenAnnotator.cpp
@@ -947,6 +947,12 @@
Tok->setType(TT_CSharpNamedArgumentColon);
break;
}
+ } else if (Style.isVerilog() && Tok->isNot(TT_BinaryOperator)) {
+ if (Keywords.isVerilogEnd(*Tok->Previous) ||
+ Keywords.isVerilogBegin(*Tok->Previous)) {
+ Tok->setType(TT_VerilogBlockLabelColon);
+ }
+ break;
}
if (Line.First->isOneOf(Keywords.kw_module, Keywords.kw_import) ||
Line.First->startsSequence(tok::kw_export, Keywords.kw_module) ||
Index: clang/lib/Format/FormatToken.h
===================================================================
--- clang/lib/Format/FormatToken.h
+++ clang/lib/Format/FormatToken.h
@@ -135,6 +135,8 @@
TYPE(UnaryOperator) \
TYPE(UnionLBrace) \
TYPE(UntouchableMacroFunc) \
+ /* like in begin : block */ \
+ TYPE(VerilogBlockLabelColon) \
/* for the base in a number literal, not including the quote */ \
TYPE(VerilogNumberBase) \
TYPE(Unknown)
@@ -995,6 +997,7 @@
kw_when = &IdentTable.get("when");
kw_where = &IdentTable.get("where");
+ // Verilog keywords
kw_always = &IdentTable.get("always");
kw_always_comb = &IdentTable.get("always_comb");
kw_always_ff = &IdentTable.get("always_ff");
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