This revision was automatically updated to reflect the committed changes.
Closed by commit rG7d8ae9f755d7: [NFC][PowerPC] Add missing NOCOMPAT checks for
builtins-ppc-xlcompat.c (authored by lei).
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D131622/new/
https://reviews.llvm.org/D131622
Files:
clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c
Index: clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c
===================================================================
--- clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c
@@ -21,29 +21,38 @@
void test() {
// CHECK-LABEL: @test(
// CHECK-NEXT: entry:
-// CHECK-LE-LABEL: @test(
-// CHECK-LE-NEXT: entry:
+// NOCOMPAT-LABEL: @test(
+// NOCOMPAT-NEXT: entry:
res_vf = vec_ctf(vsll, 4);
// CHECK: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vsll, align 16
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.ppc.vsx.xvcvsxdsp(<2 x
i64> [[TMP0]])
// CHECK-NEXT: fmul <4 x float> [[TMP1]], <float 6.250000e-02, float
6.250000e-02, float 6.250000e-02, float 6.250000e-02>
+// NOCOMPAT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vsll, align 16
+// NOCOMPAT-NEXT: [[CONV:%.*]] = sitofp <2 x i64> [[TMP0]] to <2 x double>
+// NOCOMPAT-NEXT: fmul <2 x double> [[CONV]], <double 6.250000e-02, double
6.250000e-02>
res_vf = vec_ctf(vull, 4);
// CHECK: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* @vull, align 16
// CHECK-NEXT: [[TMP3:%.*]] = call <4 x float> @llvm.ppc.vsx.xvcvuxdsp(<2 x
i64> [[TMP2]])
// CHECK-NEXT: fmul <4 x float> [[TMP3]], <float 6.250000e-02, float
6.250000e-02, float 6.250000e-02, float 6.250000e-02>
+// NOCOMPAT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* @vull, align 16
+// NOCOMPAT-NEXT: [[CONV1:%.*]] = uitofp <2 x i64> [[TMP2]] to <2 x double>
+// NOCOMPAT-NEXT: fmul <2 x double> [[CONV1]], <double 6.250000e-02, double
6.250000e-02>
res_vsll = vec_cts(vd, 4);
// CHECK: [[TMP4:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
// CHECK-NEXT: fmul <2 x double> [[TMP4]], <double 1.600000e+01, double
1.600000e+01>
// CHECK: call <4 x i32> @llvm.ppc.vsx.xvcvdpsxws(<2 x double>
+// NOCOMPAT: [[TMP4:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
+// NOCOMPAT-NEXT: fmul <2 x double> [[TMP4]], <double 1.600000e+01, double
1.600000e+01>
res_vull = vec_ctu(vd, 4);
// CHECK: [[TMP8:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
// CHECK-NEXT: fmul <2 x double> [[TMP8]], <double 1.600000e+01, double
1.600000e+01>
// CHECK: call <4 x i32> @llvm.ppc.vsx.xvcvdpuxws(<2 x double>
-// NONCOMPAT: call <4 x i32> @llvm.ppc.vsx.xvcvdpuxws(<2 x double>
+// NOCOMPAT: [[TMP7:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
+// NOCOMPAT-NEXT: fmul <2 x double> [[TMP7]], <double 1.600000e+01, double
1.600000e+01>
res_vd = vec_round(vd);
// CHECK: call double @llvm.ppc.readflm()
Index: clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c
===================================================================
--- clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c
+++ clang/test/CodeGen/PowerPC/builtins-ppc-xlcompat.c
@@ -21,29 +21,38 @@
void test() {
// CHECK-LABEL: @test(
// CHECK-NEXT: entry:
-// CHECK-LE-LABEL: @test(
-// CHECK-LE-NEXT: entry:
+// NOCOMPAT-LABEL: @test(
+// NOCOMPAT-NEXT: entry:
res_vf = vec_ctf(vsll, 4);
// CHECK: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vsll, align 16
// CHECK-NEXT: [[TMP1:%.*]] = call <4 x float> @llvm.ppc.vsx.xvcvsxdsp(<2 x i64> [[TMP0]])
// CHECK-NEXT: fmul <4 x float> [[TMP1]], <float 6.250000e-02, float 6.250000e-02, float 6.250000e-02, float 6.250000e-02>
+// NOCOMPAT: [[TMP0:%.*]] = load <2 x i64>, <2 x i64>* @vsll, align 16
+// NOCOMPAT-NEXT: [[CONV:%.*]] = sitofp <2 x i64> [[TMP0]] to <2 x double>
+// NOCOMPAT-NEXT: fmul <2 x double> [[CONV]], <double 6.250000e-02, double 6.250000e-02>
res_vf = vec_ctf(vull, 4);
// CHECK: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* @vull, align 16
// CHECK-NEXT: [[TMP3:%.*]] = call <4 x float> @llvm.ppc.vsx.xvcvuxdsp(<2 x i64> [[TMP2]])
// CHECK-NEXT: fmul <4 x float> [[TMP3]], <float 6.250000e-02, float 6.250000e-02, float 6.250000e-02, float 6.250000e-02>
+// NOCOMPAT: [[TMP2:%.*]] = load <2 x i64>, <2 x i64>* @vull, align 16
+// NOCOMPAT-NEXT: [[CONV1:%.*]] = uitofp <2 x i64> [[TMP2]] to <2 x double>
+// NOCOMPAT-NEXT: fmul <2 x double> [[CONV1]], <double 6.250000e-02, double 6.250000e-02>
res_vsll = vec_cts(vd, 4);
// CHECK: [[TMP4:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
// CHECK-NEXT: fmul <2 x double> [[TMP4]], <double 1.600000e+01, double 1.600000e+01>
// CHECK: call <4 x i32> @llvm.ppc.vsx.xvcvdpsxws(<2 x double>
+// NOCOMPAT: [[TMP4:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
+// NOCOMPAT-NEXT: fmul <2 x double> [[TMP4]], <double 1.600000e+01, double 1.600000e+01>
res_vull = vec_ctu(vd, 4);
// CHECK: [[TMP8:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
// CHECK-NEXT: fmul <2 x double> [[TMP8]], <double 1.600000e+01, double 1.600000e+01>
// CHECK: call <4 x i32> @llvm.ppc.vsx.xvcvdpuxws(<2 x double>
-// NONCOMPAT: call <4 x i32> @llvm.ppc.vsx.xvcvdpuxws(<2 x double>
+// NOCOMPAT: [[TMP7:%.*]] = load <2 x double>, <2 x double>* @vd, align 16
+// NOCOMPAT-NEXT: fmul <2 x double> [[TMP7]], <double 1.600000e+01, double 1.600000e+01>
res_vd = vec_round(vd);
// CHECK: call double @llvm.ppc.readflm()
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