jrtc27 added inline comments.
================
Comment at: llvm/lib/Target/RISCV/RISCV.td:509-517
+class RISCVProcessorModelPROC<string enum, string enum_features, string
default_march> {
+ string Enum = enum;
+ string EnumFeatures = enum_features;
+ string DefaultMarch = default_march;
+}
+
+class RISCVProcessorModelTUNE_PROC<string enum> {
----------------
Given RISCVProcessorModelTUNE_PROC is a subset of RISCVProcessorModelPROC the
latter should inherit from the former. Also since every use is also inheriting
from ProcessorModel why not make RISCVProcessorModelTUNE_PROC itself inherit
from ProcessorModel?
================
Comment at: llvm/lib/Target/RISCV/RISCV.td:519
+
+def : ProcessorModel<"generic-rv32", NoSchedModel, [Feature32Bit]>,
RISCVProcessorModelPROC<"GENERIC_RV32", "FK_NONE", "">;
+def : ProcessorModel<"generic-rv64", NoSchedModel, [Feature64Bit]>,
RISCVProcessorModelPROC<"GENERIC_RV64", "FK_64BIT", "">;
----------------
This would be more natural in TableGen as `def GENERIC_RV32 : ...` and dropping
the Enum field.
Repository:
rG LLVM Github Monorepo
CHANGES SINCE LAST ACTION
https://reviews.llvm.org/D137517/new/
https://reviews.llvm.org/D137517
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