Author: Brad Smith Date: 2023-01-12T09:08:05-05:00 New Revision: a5c9a51bf456a505386660d9be4c641fc804b7fe
URL: https://github.com/llvm/llvm-project/commit/a5c9a51bf456a505386660d9be4c641fc804b7fe DIFF: https://github.com/llvm/llvm-project/commit/a5c9a51bf456a505386660d9be4c641fc804b7fe.diff LOG: [mips][clang] Do not define __GCC_HAVE_SYNC_COMPARE_AND_SWAP macros for MIPS-I Do not define __GCC_HAVE_SYNC_COMPARE_AND_SWAP macros for MIPS-I Reviewed By: MaskRay Differential Revision: https://reviews.llvm.org/D141182 Added: Modified: clang/lib/Basic/Targets/Mips.cpp clang/test/Preprocessor/predefined-macros.c Removed: ################################################################################ diff --git a/clang/lib/Basic/Targets/Mips.cpp b/clang/lib/Basic/Targets/Mips.cpp index 2fc7572309d59..01b2e4e57a1c2 100644 --- a/clang/lib/Basic/Targets/Mips.cpp +++ b/clang/lib/Basic/Targets/Mips.cpp @@ -195,11 +195,11 @@ void MipsTargetInfo::getTargetDefines(const LangOptions &Opts, if (StringRef(CPU).startswith("octeon")) Builder.defineMacro("__OCTEON__"); - // These shouldn't be defined for MIPS-I but there's no need to check - // for that since MIPS-I isn't supported. - Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); - Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); - Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); + if (CPU != "mips1") { + Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1"); + Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2"); + Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4"); + } // 32-bit MIPS processors don't have the necessary lld/scd instructions // found in 64-bit processors. In the case of O32 on a 64-bit processor, diff --git a/clang/test/Preprocessor/predefined-macros.c b/clang/test/Preprocessor/predefined-macros.c index 897145516c52c..d77b699674af4 100644 --- a/clang/test/Preprocessor/predefined-macros.c +++ b/clang/test/Preprocessor/predefined-macros.c @@ -118,12 +118,15 @@ // RUN: | FileCheck -match-full-lines %s --check-prefix=CHECK-SYNC_CAS_ARMv6 // CHECK-SYNC_CAS_ARMv6-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP // +// RUN: %clang_cc1 %s -E -dM -o - -triple mips -target-cpu mips1 \ +// RUN: | FileCheck -match-full-lines %s --check-prefix=CHECK-SYNC_CAS_MIPS32_MIPS1 // RUN: %clang_cc1 %s -E -dM -o - -triple mips -target-cpu mips2 \ // RUN: | FileCheck -match-full-lines %s --check-prefix=CHECK-SYNC_CAS_MIPS \ // RUN: --check-prefix=CHECK-SYNC_CAS_MIPS32 // RUN: %clang_cc1 %s -E -dM -o - -triple mips64 -target-cpu mips3 \ // RUN: | FileCheck -match-full-lines %s --check-prefix=CHECK-SYNC_CAS_MIPS \ // RUN: --check-prefix=CHECK-SYNC_CAS_MIPS64 +// CHECK-SYNC_CAS_MIPS32_MIPS1-NOT: __GCC_HAVE_SYNC_COMPARE_AND_SWAP // CHECK-SYNC_CAS_MIPS: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_1 1 // CHECK-SYNC_CAS_MIPS: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_2 1 // CHECK-SYNC_CAS_MIPS: #define __GCC_HAVE_SYNC_COMPARE_AND_SWAP_4 1 _______________________________________________ cfe-commits mailing list cfe-commits@lists.llvm.org https://lists.llvm.org/cgi-bin/mailman/listinfo/cfe-commits
