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Repository:
rG LLVM Github Monorepo
https://reviews.llvm.org/D141666
Files:
clang/lib/Driver/ToolChains/Arch/RISCV.cpp
clang/lib/Driver/ToolChains/BareMetal.cpp
clang/lib/Driver/ToolChains/Gnu.cpp
clang/test/Driver/baremetal.cpp
clang/test/Driver/riscv-default-features.c
clang/test/Driver/riscv-gnutools.c
llvm/lib/Support/RISCVISAInfo.cpp
llvm/lib/Target/RISCV/RISCV.td
llvm/lib/Target/RISCV/RISCVISelLowering.cpp
llvm/lib/Target/RISCV/RISCVInstrInfo.td
llvm/test/CodeGen/RISCV/attributes.ll
llvm/test/CodeGen/RISCV/get-register-noreserve.ll
llvm/test/CodeGen/RISCV/readcyclecounter.ll
llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir
llvm/test/CodeGen/RISCV/rvv/scalar-stack-align.ll
llvm/test/CodeGen/RISCV/rvv/vscale-power-of-two.ll
llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll
llvm/test/CodeGen/RISCV/vlenb.ll
llvm/test/MC/RISCV/Ztso.s
llvm/test/MC/RISCV/csr-aliases.s
llvm/test/MC/RISCV/deprecated-csr-names.s
llvm/test/MC/RISCV/hypervisor-csr-names.s
llvm/test/MC/RISCV/machine-csr-names.s
llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
llvm/test/MC/RISCV/rv32-machine-csr-names.s
llvm/test/MC/RISCV/rv32-supervisor-csr-names.s
llvm/test/MC/RISCV/rv32-user-csr-names.s
llvm/test/MC/RISCV/rv32e-valid.s
llvm/test/MC/RISCV/rv32i-aliases-valid.s
llvm/test/MC/RISCV/rv32i-invalid.s
llvm/test/MC/RISCV/rv32i-valid.s
llvm/test/MC/RISCV/rv64-machine-csr-names.s
llvm/test/MC/RISCV/rv64-user-csr-names.s
llvm/test/MC/RISCV/rvf-user-csr-names.s
llvm/test/MC/RISCV/rvi-aliases-valid.s
llvm/test/MC/RISCV/rvk-user-csr-name.s
llvm/test/MC/RISCV/supervisor-csr-names.s
llvm/test/MC/RISCV/user-csr-names.s
Index: llvm/test/MC/RISCV/user-csr-names.s
===================================================================
--- llvm/test/MC/RISCV/user-csr-names.s
+++ llvm/test/MC/RISCV/user-csr-names.s
@@ -1,13 +1,13 @@
-# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicsr -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
-# RUN: | llvm-objdump -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zicsr < %s \
+# RUN: | llvm-objdump -d --mattr=+zicsr - \
# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s
#
-# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zicsr -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
-# RUN: | llvm-objdump -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zicsr < %s \
+# RUN: | llvm-objdump -d --mattr=+zicsr - \
# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s
##################################
Index: llvm/test/MC/RISCV/supervisor-csr-names.s
===================================================================
--- llvm/test/MC/RISCV/supervisor-csr-names.s
+++ llvm/test/MC/RISCV/supervisor-csr-names.s
@@ -1,13 +1,13 @@
-# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicsr -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
-# RUN: | llvm-objdump -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zicsr < %s \
+# RUN: | llvm-objdump -d --mattr=+zicsr - \
# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s
#
-# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zicsr -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
-# RUN: | llvm-objdump -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zicsr < %s \
+# RUN: | llvm-objdump -d --mattr=+zicsr - \
# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s
##################################
Index: llvm/test/MC/RISCV/rvk-user-csr-name.s
===================================================================
--- llvm/test/MC/RISCV/rvk-user-csr-name.s
+++ llvm/test/MC/RISCV/rvk-user-csr-name.s
@@ -1,13 +1,13 @@
-# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -mattr=+f -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -mattr=+zicsr,+f -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zkr < %s \
-# RUN: | llvm-objdump -d --mattr=+zkr - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zkr,+zicsr < %s \
+# RUN: | llvm-objdump -d --mattr=+zkr,+zicsr - \
# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s
#
-# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -mattr=+f -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -mattr=+zicsr,+f -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zkr < %s \
-# RUN: | llvm-objdump -d --mattr=+zkr - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zkr,+zicsr < %s \
+# RUN: | llvm-objdump -d --mattr=+zkr,+zicsr - \
# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s
##################################
Index: llvm/test/MC/RISCV/rvi-aliases-valid.s
===================================================================
--- llvm/test/MC/RISCV/rvi-aliases-valid.s
+++ llvm/test/MC/RISCV/rvi-aliases-valid.s
@@ -1,22 +1,22 @@
-# RUN: llvm-mc %s -triple=riscv32 -M no-aliases \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicsr -M no-aliases \
# RUN: | FileCheck -check-prefixes=CHECK-S-NOALIAS,CHECK-S-OBJ-NOALIAS %s
-# RUN: llvm-mc %s -triple=riscv32 \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicsr \
# RUN: | FileCheck -check-prefixes=CHECK-S,CHECK-S-OBJ %s
-# RUN: llvm-mc %s -triple=riscv64 -M no-aliases \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zicsr -M no-aliases \
# RUN: | FileCheck -check-prefixes=CHECK-S-NOALIAS,CHECK-S-OBJ-NOALIAS %s
-# RUN: llvm-mc %s -triple=riscv64 \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zicsr \
# RUN: | FileCheck -check-prefixes=CHECK-S,CHECK-S-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
-# RUN: | llvm-objdump -d -r -M no-aliases - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zicsr < %s \
+# RUN: | llvm-objdump -d -r --mattr=+zicsr -M no-aliases - \
# RUN: | FileCheck -check-prefixes=CHECK-OBJ-NOALIAS,CHECK-S-OBJ-NOALIAS %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
-# RUN: | llvm-objdump -d -r - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zicsr < %s \
+# RUN: | llvm-objdump -d -r --mattr=+zicsr - \
# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-S-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
-# RUN: | llvm-objdump -d -r -M no-aliases - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zicsr < %s \
+# RUN: | llvm-objdump -d -r --mattr=+zicsr -M no-aliases - \
# RUN: | FileCheck -check-prefixes=CHECK-OBJ-NOALIAS,CHECK-S-OBJ-NOALIAS %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
-# RUN: | llvm-objdump -d -r - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zicsr < %s \
+# RUN: | llvm-objdump -d -r --mattr=+zicsr - \
# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-S-OBJ %s
# The following check prefixes are used in this test:
Index: llvm/test/MC/RISCV/rvf-user-csr-names.s
===================================================================
--- llvm/test/MC/RISCV/rvf-user-csr-names.s
+++ llvm/test/MC/RISCV/rvf-user-csr-names.s
@@ -1,19 +1,19 @@
-# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -mattr=+f -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -mattr=+f,+zicsr -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \
-# RUN: | llvm-objdump -d --mattr=+f - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f,+zicsr < %s \
+# RUN: | llvm-objdump -d --mattr=+f,+zicsr - \
# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \
-# RUN: | llvm-objdump -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f,+zicsr < %s \
+# RUN: | llvm-objdump -d --mattr=+zicsr - \
# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS-NO-F %s
#
-# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -mattr=+f -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -mattr=+f,+zicsr -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \
-# RUN: | llvm-objdump -d --mattr=+f - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f,+zicsr < %s \
+# RUN: | llvm-objdump -d --mattr=+f,+zicsr - \
# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \
-# RUN: | llvm-objdump -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f,+zicsr < %s \
+# RUN: | llvm-objdump -d --mattr=+zicsr - \
# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS-NO-F %s
##################################
Index: llvm/test/MC/RISCV/rv64-user-csr-names.s
===================================================================
--- llvm/test/MC/RISCV/rv64-user-csr-names.s
+++ llvm/test/MC/RISCV/rv64-user-csr-names.s
@@ -1,7 +1,7 @@
-# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zicsr -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
-# RUN: | llvm-objdump -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zicsr < %s \
+# RUN: | llvm-objdump -d --mattr=+zicsr - \
# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s
# These user mode CSR register names are RV32 only, but RV64
Index: llvm/test/MC/RISCV/rv64-machine-csr-names.s
===================================================================
--- llvm/test/MC/RISCV/rv64-machine-csr-names.s
+++ llvm/test/MC/RISCV/rv64-machine-csr-names.s
@@ -1,7 +1,7 @@
-# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zicsr -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
-# RUN: | llvm-objdump -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zicsr < %s \
+# RUN: | llvm-objdump -d --mattr=+zicsr - \
# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s
# These machine mode CSR register names are RV32 only, but RV64
Index: llvm/test/MC/RISCV/rv32i-valid.s
===================================================================
--- llvm/test/MC/RISCV/rv32i-valid.s
+++ llvm/test/MC/RISCV/rv32i-valid.s
@@ -1,12 +1,12 @@
-# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicsr,+zifencei -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc %s -triple riscv64 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple riscv64 -mattr=+zicsr,+zifencei -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 < %s \
-# RUN: | llvm-objdump -M no-aliases -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+zicsr,+zifencei < %s \
+# RUN: | llvm-objdump -M no-aliases -d -r --mattr=+zicsr,+zifencei - \
# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-OBJ32,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv64 < %s \
-# RUN: | llvm-objdump -M no-aliases -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv64 -mattr=+zicsr,+zifencei < %s \
+# RUN: | llvm-objdump -M no-aliases -d -r --mattr=+zicsr,+zifencei - \
# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-OBJ64,CHECK-ASM-AND-OBJ %s
.equ CONST, 30
Index: llvm/test/MC/RISCV/rv32i-invalid.s
===================================================================
--- llvm/test/MC/RISCV/rv32i-invalid.s
+++ llvm/test/MC/RISCV/rv32i-invalid.s
@@ -1,4 +1,4 @@
-# RUN: not llvm-mc -triple riscv32 %s 2>&1 | FileCheck %s
+# RUN: not llvm-mc -triple riscv32 -mattr=+zicsr %s 2>&1 | FileCheck %s
# Out of range immediates
## fencearg
Index: llvm/test/MC/RISCV/rv32i-aliases-valid.s
===================================================================
--- llvm/test/MC/RISCV/rv32i-aliases-valid.s
+++ llvm/test/MC/RISCV/rv32i-aliases-valid.s
@@ -1,12 +1,12 @@
-# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicsr -riscv-no-aliases \
# RUN: | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-INST %s
-# RUN: llvm-mc %s -triple=riscv32 \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicsr \
# RUN: | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-ALIAS %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
-# RUN: | llvm-objdump -M no-aliases -d -r - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zicsr < %s \
+# RUN: | llvm-objdump -M no-aliases -d -r --mattr=+zicsr - \
# RUN: | FileCheck -check-prefixes=CHECK-OBJ-NOALIAS,CHECK-EXPAND,CHECK-INST %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
-# RUN: | llvm-objdump -d -r - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zicsr < %s \
+# RUN: | llvm-objdump -d -r --mattr=+zicsr - \
# RUN: | FileCheck -check-prefixes=CHECK-EXPAND,CHECK-ALIAS %s
# The following check prefixes are used in this test:
Index: llvm/test/MC/RISCV/rv32e-valid.s
===================================================================
--- llvm/test/MC/RISCV/rv32e-valid.s
+++ llvm/test/MC/RISCV/rv32e-valid.s
@@ -1,7 +1,7 @@
-# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -mattr=+e -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -mattr=+e,+zicsr,+zifencei -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-ASM,CHECK-ASM-AND-OBJ %s
-# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+e < %s \
-# RUN: | llvm-objdump -M no-aliases -d -r - \
+# RUN: llvm-mc -filetype=obj -triple=riscv32 -mattr=+e,+zicsr,+zifencei < %s \
+# RUN: | llvm-objdump -M no-aliases -d -r --mattr=+zicsr,+zifencei - \
# RUN: | FileCheck -check-prefixes=CHECK-OBJ,CHECK-ASM-AND-OBJ %s
# This file provides a basic test for RV32E, checking that the expected
Index: llvm/test/MC/RISCV/rv32-user-csr-names.s
===================================================================
--- llvm/test/MC/RISCV/rv32-user-csr-names.s
+++ llvm/test/MC/RISCV/rv32-user-csr-names.s
@@ -1,7 +1,7 @@
-# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicsr -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
-# RUN: | llvm-objdump -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zicsr < %s \
+# RUN: | llvm-objdump -d --mattr=+zicsr - \
# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s
##################################
Index: llvm/test/MC/RISCV/rv32-supervisor-csr-names.s
===================================================================
--- llvm/test/MC/RISCV/rv32-supervisor-csr-names.s
+++ llvm/test/MC/RISCV/rv32-supervisor-csr-names.s
@@ -1,7 +1,7 @@
-# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicsr -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
-# RUN: | llvm-objdump -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zicsr < %s \
+# RUN: | llvm-objdump -d --mattr=+zicsr - \
# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s
##################################
Index: llvm/test/MC/RISCV/rv32-machine-csr-names.s
===================================================================
--- llvm/test/MC/RISCV/rv32-machine-csr-names.s
+++ llvm/test/MC/RISCV/rv32-machine-csr-names.s
@@ -1,7 +1,7 @@
-# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicsr -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
-# RUN: | llvm-objdump -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zicsr < %s \
+# RUN: | llvm-objdump -d --mattr=+zicsr - \
# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s
######################################
Index: llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
===================================================================
--- llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
+++ llvm/test/MC/RISCV/rv32-hypervisor-csr-names.s
@@ -1,7 +1,7 @@
-# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -mattr=+zicsr -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
-# RUN: | llvm-objdump -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zicsr < %s \
+# RUN: | llvm-objdump -d --mattr=+zicsr - \
# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s
##################################
Index: llvm/test/MC/RISCV/machine-csr-names.s
===================================================================
--- llvm/test/MC/RISCV/machine-csr-names.s
+++ llvm/test/MC/RISCV/machine-csr-names.s
@@ -1,13 +1,13 @@
-# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicsr -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
-# RUN: | llvm-objdump -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zicsr < %s \
+# RUN: | llvm-objdump -d --mattr=+zicsr - \
# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s
#
-# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zicsr -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
-# RUN: | llvm-objdump -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zicsr < %s \
+# RUN: | llvm-objdump -d --mattr=+zicsr - \
# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s
##################################
Index: llvm/test/MC/RISCV/hypervisor-csr-names.s
===================================================================
--- llvm/test/MC/RISCV/hypervisor-csr-names.s
+++ llvm/test/MC/RISCV/hypervisor-csr-names.s
@@ -1,13 +1,13 @@
-# RUN: llvm-mc %s -triple=riscv32 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+zicsr -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 < %s \
-# RUN: | llvm-objdump -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+zicsr < %s \
+# RUN: | llvm-objdump -d --mattr=+zicsr - \
# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s
#
-# RUN: llvm-mc %s -triple=riscv64 -riscv-no-aliases -show-encoding \
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+zicsr -riscv-no-aliases -show-encoding \
# RUN: | FileCheck -check-prefixes=CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 < %s \
-# RUN: | llvm-objdump -d - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+zicsr < %s \
+# RUN: | llvm-objdump -d --mattr=+zicsr - \
# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s
##################################
Index: llvm/test/MC/RISCV/deprecated-csr-names.s
===================================================================
--- llvm/test/MC/RISCV/deprecated-csr-names.s
+++ llvm/test/MC/RISCV/deprecated-csr-names.s
@@ -1,16 +1,16 @@
-# RUN: llvm-mc -triple riscv32 -riscv-no-aliases -show-encoding %s \
+# RUN: llvm-mc -triple riscv32 -mattr=+zicsr -riscv-no-aliases -show-encoding %s \
# RUN: | FileCheck -check-prefixes CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype obj -triple riscv32 %s \
-# RUN: | llvm-objdump -d - \
+# RUN: llvm-mc -filetype obj -triple riscv32 -mattr=+zicsr %s \
+# RUN: | llvm-objdump -d --mattr=+zicsr - \
# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s
-# RUN: llvm-mc -triple riscv64 -riscv-no-aliases -show-encoding %s \
+# RUN: llvm-mc -triple riscv64 -mattr=+zicsr -riscv-no-aliases -show-encoding %s \
# RUN: | FileCheck -check-prefixes CHECK-INST,CHECK-ENC %s
-# RUN: llvm-mc -filetype obj -triple riscv64 %s \
-# RUN: | llvm-objdump -d - \
+# RUN: llvm-mc -filetype obj -triple riscv64 -mattr=+zicsr %s \
+# RUN: | llvm-objdump -d --mattr=+zicsr - \
# RUN: | FileCheck -check-prefix=CHECK-INST-ALIAS %s
-# RUN: llvm-mc -triple riscv32 %s 2>&1 | FileCheck -check-prefix CHECK-WARN %s
+# RUN: llvm-mc -triple riscv32 -mattr=+zicsr %s 2>&1 | FileCheck -check-prefix CHECK-WARN %s
# sbadaddr
# name
Index: llvm/test/MC/RISCV/csr-aliases.s
===================================================================
--- llvm/test/MC/RISCV/csr-aliases.s
+++ llvm/test/MC/RISCV/csr-aliases.s
@@ -1,39 +1,39 @@
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \
-# RUN: | llvm-objdump -d --mattr=+f -M no-aliases - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f,+zicsr < %s \
+# RUN: | llvm-objdump -d --mattr=+f,+zicsr -M no-aliases - \
# RUN: | FileCheck -check-prefix=CHECK-INST %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \
-# RUN: | llvm-objdump -d --mattr=+f - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f,+zicsr < %s \
+# RUN: | llvm-objdump -d --mattr=+f,+zicsr - \
# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \
-# RUN: | llvm-objdump -d --mattr=+f - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f,+zicsr < %s \
+# RUN: | llvm-objdump -d --mattr=+f,+zicsr - \
# RUN: | FileCheck -check-prefix=CHECK-EXT-F %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=-f < %s \
-# RUN: | llvm-objdump -d --mattr=+f - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=-f,+zicsr < %s \
+# RUN: | llvm-objdump -d --mattr=+f,+zicsr - \
# RUN: | FileCheck -check-prefix=CHECK-EXT-F %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=-f < %s \
-# RUN: | llvm-objdump -d --mattr=-f - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=-f,+zicsr < %s \
+# RUN: | llvm-objdump -d --mattr=-f,+zicsr - \
# RUN: | FileCheck -check-prefix=CHECK-EXT-F-OFF %s
-# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f < %s \
-# RUN: | llvm-objdump -d --mattr=-f - \
+# RUN: llvm-mc -filetype=obj -triple riscv32 -mattr=+f,+zicsr < %s \
+# RUN: | llvm-objdump -d --mattr=-f,+zicsr - \
# RUN: | FileCheck -check-prefix=CHECK-EXT-F-OFF %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \
-# RUN: | llvm-objdump -d --mattr=+f -M no-aliases - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f,+zicsr < %s \
+# RUN: | llvm-objdump -d --mattr=+f,+zicsr -M no-aliases - \
# RUN: | FileCheck -check-prefix=CHECK-INST %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \
-# RUN: | llvm-objdump -d --mattr=+f - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f,+zicsr < %s \
+# RUN: | llvm-objdump -d --mattr=+f,+zicsr - \
# RUN: | FileCheck -check-prefix=CHECK-ALIAS %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \
-# RUN: | llvm-objdump -d --mattr=+f - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f,+zicsr < %s \
+# RUN: | llvm-objdump -d --mattr=+f,+zicsr - \
# RUN: | FileCheck -check-prefix=CHECK-EXT-F %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=-f < %s \
-# RUN: | llvm-objdump -d --mattr=+f - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=-f,+zicsr < %s \
+# RUN: | llvm-objdump -d --mattr=+f,+zicsr - \
# RUN: | FileCheck -check-prefix=CHECK-EXT-F %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=-f < %s \
-# RUN: | llvm-objdump -d --mattr=-f - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=-f,+zicsr < %s \
+# RUN: | llvm-objdump -d --mattr=-f,+zicsr - \
# RUN: | FileCheck -check-prefix=CHECK-EXT-F-OFF %s
-# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f < %s \
-# RUN: | llvm-objdump -d --mattr=-f - \
+# RUN: llvm-mc -filetype=obj -triple riscv64 -mattr=+f,+zicsr < %s \
+# RUN: | llvm-objdump -d --mattr=-f,+zicsr - \
# RUN: | FileCheck -check-prefix=CHECK-EXT-F-OFF %s
Index: llvm/test/MC/RISCV/Ztso.s
===================================================================
--- llvm/test/MC/RISCV/Ztso.s
+++ llvm/test/MC/RISCV/Ztso.s
@@ -1,5 +1,5 @@
-# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-ztso -riscv-no-aliases 2>&1 | FileCheck %s
-# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-ztso -riscv-no-aliases 2>&1 | FileCheck %s
+# RUN: llvm-mc %s -triple=riscv64 -mattr=+experimental-ztso,+zifencei -riscv-no-aliases 2>&1 | FileCheck %s
+# RUN: llvm-mc %s -triple=riscv32 -mattr=+experimental-ztso,+zifencei -riscv-no-aliases 2>&1 | FileCheck %s
# Note: Ztso doesn't add or remove any instructions, so this is basically
# just checking that a) we accepted the attribute name, and b) codegen did
Index: llvm/test/CodeGen/RISCV/vlenb.ll
===================================================================
--- llvm/test/CodeGen/RISCV/vlenb.ll
+++ llvm/test/CodeGen/RISCV/vlenb.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -O3 < %s -mtriple=riscv32 | FileCheck %s
+; RUN: llc -O3 < %s -mtriple=riscv32 -mattr=+zicsr | FileCheck %s
; These tests demonstrate optimizations involving copies from VLENB.
Index: llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll
+++ llvm/test/CodeGen/RISCV/rvv/zvlsseg-zero-vl.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+zve32x \
+; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+zve32x \
; RUN: -verify-machineinstrs < %s | FileCheck %s
; Make sure we don't select a 0 vl to X0 in the custom isel handlers we use
Index: llvm/test/CodeGen/RISCV/rvv/vscale-power-of-two.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/vscale-power-of-two.ll
+++ llvm/test/CodeGen/RISCV/rvv/vscale-power-of-two.ll
@@ -1,6 +1,6 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv64 -mattr=+v,+m -verify-machineinstrs < %s | FileCheck %s
-; RUN: llc -mtriple=riscv64 -mattr=+Zve64x,+m -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+v,+m -verify-machineinstrs < %s | FileCheck %s
+; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+Zve64x,+m -verify-machineinstrs < %s | FileCheck %s
declare i64 @llvm.vscale.i64()
define i64 @vscale_lshr(i64 %TC) {
Index: llvm/test/CodeGen/RISCV/rvv/scalar-stack-align.ll
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/scalar-stack-align.ll
+++ llvm/test/CodeGen/RISCV/rvv/scalar-stack-align.ll
@@ -1,11 +1,11 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -mattr=+zve64x -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+zicsr,+zve64x -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefix=RV32
-; RUN: llc -mtriple=riscv64 -mattr=+zve64x -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+zve64x -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefix=RV64
-; RUN: llc -mtriple=riscv32 -mattr=+v -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+zicsr,+v -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefix=RV32
-; RUN: llc -mtriple=riscv64 -mattr=+v -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+zicsr,+v -verify-machineinstrs < %s \
; RUN: | FileCheck %s --check-prefix=RV64
; FIXME: We are over-aligning the stack on V, wasting stack space.
Index: llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir
===================================================================
--- llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir
+++ llvm/test/CodeGen/RISCV/rvv/rvv-stack-align.mir
@@ -1,11 +1,11 @@
# NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-# RUN: llc -mtriple riscv32 -mattr=+zve64x -start-before=prologepilog -o - \
+# RUN: llc -mtriple riscv32 -mattr=+zicsr,+zve64x -start-before=prologepilog -o - \
# RUN: -verify-machineinstrs %s | FileCheck %s --check-prefix=RV32
-# RUN: llc -mtriple riscv32 -mattr=+v -start-before=prologepilog -o - \
+# RUN: llc -mtriple riscv32 -mattr=+zicsr,+v -start-before=prologepilog -o - \
# RUN: -verify-machineinstrs %s | FileCheck %s --check-prefix=RV32
-# RUN: llc -mtriple riscv64 -mattr=+zve64x -start-before=prologepilog -o - \
+# RUN: llc -mtriple riscv64 -mattr=+zicsr,+zve64x -start-before=prologepilog -o - \
# RUN: -verify-machineinstrs %s | FileCheck %s --check-prefix=RV64
-# RUN: llc -mtriple riscv64 -mattr=+v -start-before=prologepilog -o - \
+# RUN: llc -mtriple riscv64 -mattr=+zicsr,+v -start-before=prologepilog -o - \
# RUN: -verify-machineinstrs %s | FileCheck %s --check-prefix=RV64
--- |
target datalayout = "e-m:e-p:64:64-i64:64-i128:128-n64-S128"
Index: llvm/test/CodeGen/RISCV/readcyclecounter.ll
===================================================================
--- llvm/test/CodeGen/RISCV/readcyclecounter.ll
+++ llvm/test/CodeGen/RISCV/readcyclecounter.ll
@@ -1,7 +1,7 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc -mtriple=riscv32 -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv32 -mattr=+zicsr -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV32I %s
-; RUN: llc -mtriple=riscv64 -verify-machineinstrs < %s \
+; RUN: llc -mtriple=riscv64 -mattr=+zicsr -verify-machineinstrs < %s \
; RUN: | FileCheck -check-prefix=RV64I %s
; Verify that we lower @llvm.readcyclecounter() correctly.
Index: llvm/test/CodeGen/RISCV/get-register-noreserve.ll
===================================================================
--- llvm/test/CodeGen/RISCV/get-register-noreserve.ll
+++ llvm/test/CodeGen/RISCV/get-register-noreserve.ll
@@ -1,5 +1,5 @@
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
-; RUN: llc < %s -mtriple=riscv32 | FileCheck %s
+; RUN: llc < %s -mtriple=riscv32 -mattr=+zicsr | FileCheck %s
define i32 @get_stack() nounwind {
; CHECK-LABEL: get_stack:
Index: llvm/test/CodeGen/RISCV/attributes.ll
===================================================================
--- llvm/test/CodeGen/RISCV/attributes.ll
+++ llvm/test/CodeGen/RISCV/attributes.ll
@@ -92,13 +92,13 @@
; RV32ZMMUL: .attribute 5, "rv32i2p0_zmmul1p0"
; RV32MZMMUL: .attribute 5, "rv32i2p0_m2p0_zmmul1p0"
; RV32A: .attribute 5, "rv32i2p0_a2p0"
-; RV32F: .attribute 5, "rv32i2p0_f2p0"
-; RV32D: .attribute 5, "rv32i2p0_f2p0_d2p0"
+; RV32F: .attribute 5, "rv32i2p1_f2p2_zicsr2p0"
+; RV32D: .attribute 5, "rv32i2p1_f2p2_d2p2_zicsr2p0"
; RV32C: .attribute 5, "rv32i2p0_c2p0"
; RV32ZIHINTPAUSE: .attribute 5, "rv32i2p0_zihintpause2p0"
; RV32ZIHINTNTL: .attribute 5, "rv32i2p0_zihintntl0p2"
-; RV32ZFHMIN: .attribute 5, "rv32i2p0_f2p0_zfhmin1p0"
-; RV32ZFH: .attribute 5, "rv32i2p0_f2p0_zfh1p0"
+; RV32ZFHMIN: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfhmin1p0"
+; RV32ZFH: .attribute 5, "rv32i2p1_f2p2_zicsr2p0_zfh1p0"
; RV32ZBA: .attribute 5, "rv32i2p0_zba1p0"
; RV32ZBB: .attribute 5, "rv32i2p0_zbb1p0"
; RV32ZBC: .attribute 5, "rv32i2p0_zbc1p0"
@@ -109,8 +109,8 @@
; RV32ZBKB: .attribute 5, "rv32i2p0_zbkb1p0"
; RV32ZBKC: .attribute 5, "rv32i2p0_zbkc1p0"
; RV32ZBKX: .attribute 5, "rv32i2p0_zbkx1p0"
-; RV32ZKND: .attribute 5, "rv32i2p0_zknd1p0"
-; RV32ZKNE: .attribute 5, "rv32i2p0_zkne1p0"
+; RV32V: .attribute 5, "rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+; RV32COMBINED: .attribute 5, "rv32i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
; RV32ZKNH: .attribute 5, "rv32i2p0_zknh1p0"
; RV32ZKSED: .attribute 5, "rv32i2p0_zksed1p0"
; RV32ZKSH: .attribute 5, "rv32i2p0_zksh1p0"
@@ -134,13 +134,13 @@
; RV64ZMMUL: .attribute 5, "rv64i2p0_zmmul1p0"
; RV64MZMMUL: .attribute 5, "rv64i2p0_m2p0_zmmul1p0"
; RV64A: .attribute 5, "rv64i2p0_a2p0"
-; RV64F: .attribute 5, "rv64i2p0_f2p0"
-; RV64D: .attribute 5, "rv64i2p0_f2p0_d2p0"
+; RV64F: .attribute 5, "rv64i2p1_f2p2_zicsr2p0"
+; RV64D: .attribute 5, "rv64i2p1_f2p2_d2p2_zicsr2p0"
; RV64C: .attribute 5, "rv64i2p0_c2p0"
; RV64ZIHINTPAUSE: .attribute 5, "rv64i2p0_zihintpause2p0"
; RV64ZIHINTNTL: .attribute 5, "rv64i2p0_zihintntl0p2"
-; RV64ZFHMIN: .attribute 5, "rv64i2p0_f2p0_zfhmin1p0"
-; RV64ZFH: .attribute 5, "rv64i2p0_f2p0_zfh1p0"
+; RV64ZFHMIN: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfhmin1p0"
+; RV64ZFH: .attribute 5, "rv64i2p1_f2p2_zicsr2p0_zfh1p0"
; RV64ZBA: .attribute 5, "rv64i2p0_zba1p0"
; RV64ZBB: .attribute 5, "rv64i2p0_zbb1p0"
; RV64ZBC: .attribute 5, "rv64i2p0_zbc1p0"
@@ -151,8 +151,8 @@
; RV64ZBKB: .attribute 5, "rv64i2p0_zbkb1p0"
; RV64ZBKC: .attribute 5, "rv64i2p0_zbkc1p0"
; RV64ZBKX: .attribute 5, "rv64i2p0_zbkx1p0"
-; RV64ZKND: .attribute 5, "rv64i2p0_zknd1p0"
-; RV64ZKNE: .attribute 5, "rv64i2p0_zkne1p0"
+; RV64V: .attribute 5, "rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
+; RV64COMBINED: .attribute 5, "rv64i2p1_f2p2_d2p2_v1p0_zicsr2p0_zfh1p0_zbb1p0_zve32f1p0_zve32x1p0_zve64d1p0_zve64f1p0_zve64x1p0_zvl128b1p0_zvl32b1p0_zvl64b1p0"
; RV64ZKNH: .attribute 5, "rv64i2p0_zknh1p0"
; RV64ZKSED: .attribute 5, "rv64i2p0_zksed1p0"
; RV64ZKSH: .attribute 5, "rv64i2p0_zksh1p0"
Index: llvm/lib/Target/RISCV/RISCVInstrInfo.td
===================================================================
--- llvm/lib/Target/RISCV/RISCVInstrInfo.td
+++ llvm/lib/Target/RISCV/RISCVInstrInfo.td
@@ -699,11 +699,13 @@
let imm12 = {0b1000,0b0011,0b0011};
}
+let Predicates = [HasStdExtZifencei] in {
def FENCE_I : RVInstI<0b001, OPC_MISC_MEM, (outs), (ins), "fence.i", "">, Sched<[]> {
let rs1 = 0;
let rd = 0;
let imm12 = 0;
}
+} // Predicates = [HasStdExtZifencei]
def ECALL : RVInstI<0b000, OPC_SYSTEM, (outs), (ins), "ecall", "">, Sched<[WriteJmp]> {
let rs1 = 0;
@@ -746,6 +748,7 @@
} // hasSideEffects = 1, mayLoad = 0, mayStore = 0
+let Predicates = [HasStdExtZicsr] in {
def CSRRW : CSR_ir<0b001, "csrrw">;
def CSRRS : CSR_ir<0b010, "csrrs">;
def CSRRC : CSR_ir<0b011, "csrrc">;
@@ -753,6 +756,7 @@
def CSRRWI : CSR_ii<0b101, "csrrwi">;
def CSRRSI : CSR_ii<0b110, "csrrsi">;
def CSRRCI : CSR_ii<0b111, "csrrci">;
+} // Predicates = [HasStdExtZicsr]
/// RV64I instructions
@@ -976,6 +980,7 @@
def : InstAlias<"rdtimeh $rd", (CSRRS GPR:$rd, TIMEH.Encoding, X0)>;
} // Predicates = [IsRV32]
+let Predicates = [HasStdExtZicsr] in {
def : InstAlias<"csrr $rd, $csr", (CSRRS GPR:$rd, csr_sysreg:$csr, X0)>;
def : InstAlias<"csrw $csr, $rs", (CSRRW X0, csr_sysreg:$csr, GPR:$rs)>;
def : InstAlias<"csrs $csr, $rs", (CSRRS X0, csr_sysreg:$csr, GPR:$rs)>;
@@ -994,6 +999,7 @@
def : InstAlias<"csrrs $rd, $csr, $imm", (CSRRSI GPR:$rd, csr_sysreg:$csr, uimm5:$imm)>;
def : InstAlias<"csrrc $rd, $csr, $imm", (CSRRCI GPR:$rd, csr_sysreg:$csr, uimm5:$imm)>;
}
+} // Predicates = [HasStdExtZicsr]
def : InstAlias<"sfence.vma", (SFENCE_VMA X0, X0)>;
def : InstAlias<"sfence.vma $rs", (SFENCE_VMA GPR:$rs, X0)>;
@@ -1645,7 +1651,7 @@
// Helpers for defining specific operations. They are defined for each system
// register separately. Side effect is not used because dependencies are
// expressed via use-def properties.
-
+let Predicates = [HasStdExtZicsr] in {
class ReadSysReg<SysReg SR, list<Register> Regs>
: Pseudo<(outs GPR:$rd), (ins),
[(set GPR:$rd, (riscv_read_csr (XLenVT SR.Encoding)))]>,
@@ -1686,7 +1692,7 @@
let hasSideEffects = 0;
let Uses = Regs;
let Defs = Regs;
-}
+} // Predicates = [HasStdExtZicsr]
def ReadFRM : ReadSysReg<SysRegFRM, [FRM]>;
def WriteFRM : WriteSysReg<SysRegFRM, [FRM]>;
@@ -1697,6 +1703,7 @@
def ReadFFLAGS : ReadSysReg<SysRegFFLAGS, [FFLAGS]>;
def WriteFFLAGS : WriteSysReg<SysRegFFLAGS, [FFLAGS]>;
}
+}
/// Other pseudo-instructions
// Pessimistically assume the stack pointer will be clobbered
Index: llvm/lib/Target/RISCV/RISCVISelLowering.cpp
===================================================================
--- llvm/lib/Target/RISCV/RISCVISelLowering.cpp
+++ llvm/lib/Target/RISCV/RISCVISelLowering.cpp
@@ -7542,6 +7542,8 @@
SDValue RISCVTargetLowering::lowerSET_ROUNDING(SDValue Op,
SelectionDAG &DAG) const {
+ assert(Subtarget.hasStdExtZicsr() &&
+ "SET_ROUNDING can be used only with Zicsr");
const MVT XLenVT = Subtarget.getXLenVT();
SDLoc DL(Op);
SDValue Chain = Op->getOperand(0);
@@ -11556,6 +11558,8 @@
case RISCV::ReadCycleWide:
assert(!Subtarget.is64Bit() &&
"ReadCycleWrite is only to be used on riscv32");
+ assert(Subtarget.hasStdExtZicsr() &&
+ "ReadCycleWrite is only to be used with Zicsr");
return emitReadCycleWidePseudo(MI, BB);
case RISCV::Select_GPR_Using_CC_GPR:
case RISCV::Select_FPR16_Using_CC_GPR:
Index: llvm/lib/Target/RISCV/RISCV.td
===================================================================
--- llvm/lib/Target/RISCV/RISCV.td
+++ llvm/lib/Target/RISCV/RISCV.td
@@ -36,9 +36,25 @@
AssemblerPredicate<(all_of FeatureStdExtA),
"'A' (Atomic Instructions)">;
+def FeatureStdExtZicsr
+ : SubtargetFeature<"zicsr", "HasStdExtZicsr", "true",
+ "'Zicsr' (Control and Status Register (CSR) Instructions)">;
+def HasStdExtZicsr : Predicate<"Subtarget->hasStdExtZicsr()">,
+ AssemblerPredicate<(all_of FeatureStdExtZicsr),
+ "'Zicsr' (Control and Status Register (CSR) Instructions)">;
+
+def FeatureStdExtZifencei
+ : SubtargetFeature<"zifencei", "HasStdExtZifencei", "true",
+ "'Zifencei' (Instruction-Fetch Fence)">;
+
+def HasStdExtZifencei : Predicate<"Subtarget->hasStdExtZifencei()">,
+ AssemblerPredicate<(all_of FeatureStdExtZifencei),
+ "'Zifencei' (Instruction-Fetch Fence)">;
+
def FeatureStdExtF
: SubtargetFeature<"f", "HasStdExtF", "true",
- "'F' (Single-Precision Floating-Point)">;
+ "'F' (Single-Precision Floating-Point)",
+ [FeatureStdExtZicsr]>;
def HasStdExtF : Predicate<"Subtarget->hasStdExtF()">,
AssemblerPredicate<(all_of FeatureStdExtF),
"'F' (Single-Precision Floating-Point)">;
Index: llvm/lib/Support/RISCVISAInfo.cpp
===================================================================
--- llvm/lib/Support/RISCVISAInfo.cpp
+++ llvm/lib/Support/RISCVISAInfo.cpp
@@ -68,6 +68,8 @@
{"zbkb", RISCVExtensionVersion{1, 0}},
{"zbkc", RISCVExtensionVersion{1, 0}},
{"zbkx", RISCVExtensionVersion{1, 0}},
+ {"zicsr", RISCVExtensionVersion{2, 0}},
+ {"zifencei", RISCVExtensionVersion{2, 0}},
{"zknd", RISCVExtensionVersion{1, 0}},
{"zkne", RISCVExtensionVersion{1, 0}},
{"zknh", RISCVExtensionVersion{1, 0}},
Index: clang/test/Driver/riscv-gnutools.c
===================================================================
--- clang/test/Driver/riscv-gnutools.c
+++ clang/test/Driver/riscv-gnutools.c
@@ -20,8 +20,8 @@
// RUN: %clang -target riscv32-unknown-elf --gcc-toolchain=%S/Inputs/basic_riscv32_tree -mno-relax -fno-integrated-as %s -### -c \
// RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV32-NO-RELAX %s
-// CHECK-RV32IMAC-ILP32: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32" "-march" "rv32imac"
-// CHECK-RV32IMAFDC-ILP32D: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32d" "-march" "rv32imafdc"
+// CHECK-RV32IMAC-ILP32: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32" "-march" "rv32imac_zicsr_zifencei"
+// CHECK-RV32IMAFDC-ILP32D: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32d" "-march" "rv32imafdc_zicsr_zifencei"
// CHECK-RV32G-ILP32D: "{{.*}}as{{(.exe)?}}" "-mabi" "ilp32d" "-march" "rv32g"
// CHECK-RV32-NO-RELAX: "{{.*}}as{{(.exe)?}}" "{{.*}}" "-mno-relax"
@@ -44,8 +44,8 @@
// RUN: %clang -target riscv64-unknown-elf --gcc-toolchain=%S/Inputs/basic_riscv64_tree -mno-relax -mrelax -fno-integrated-as %s -### -c \
// RUN: 2>&1 | FileCheck -check-prefix=CHECK-RV64-RELAX %s
-// CHECK-RV64IMAC-LP64: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64" "-march" "rv64imac"
-// CHECK-RV64IMAFDC-LP64D: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64d" "-march" "rv64imafdc"
+// CHECK-RV64IMAC-LP64: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64" "-march" "rv64imac_zicsr_zifencei"
+// CHECK-RV64IMAFDC-LP64D: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64d" "-march" "rv64imafdc_zicsr_zifencei"
// CHECK-RV64G-LP64D: "{{.*}}as{{(.exe)?}}" "-mabi" "lp64d" "-march" "rv64g"
// CHECK-RV64-RELAX: "{{.*}}as{{(.exe)?}}"
// CHECK-RV64-RELAX-NOT: "-mno-relax"
Index: clang/test/Driver/riscv-default-features.c
===================================================================
--- clang/test/Driver/riscv-default-features.c
+++ clang/test/Driver/riscv-default-features.c
@@ -1,8 +1,8 @@
// RUN: %clang --target=riscv32-unknown-elf -S -emit-llvm %s -o - | FileCheck %s -check-prefix=RV32
// RUN: %clang --target=riscv64-unknown-elf -S -emit-llvm %s -o - | FileCheck %s -check-prefix=RV64
-// RV32: "target-features"="+32bit,+a,+c,+m,+relax,-save-restore"
-// RV64: "target-features"="+64bit,+a,+c,+m,+relax,-save-restore"
+// RV32: "target-features"="+32bit,+a,+c,+m,+relax,+zicsr,+zifencei,-save-restore"
+// RV64: "target-features"="+64bit,+a,+c,+m,+relax,+zicsr,+zifencei,-save-restore"
// Dummy function
int foo(void){
Index: clang/test/Driver/baremetal.cpp
===================================================================
--- clang/test/Driver/baremetal.cpp
+++ clang/test/Driver/baremetal.cpp
@@ -245,7 +245,7 @@
// CHECK-RV64-NDL-SAME: "-L[[RESOURCE_DIR]]{{[/\\]+}}lib{{[/\\]+}}baremetal"
// RUN: %clang %s -### 2>&1 --target=riscv64-unknown-elf \
-// RUN: -march=rv64imafdc -mabi=lp64d \
+// RUN: -march=rv64imafdc_zicsr_zifencei -mabi=lp64d \
// RUN: --sysroot=%S/Inputs/basic_riscv64_tree/riscv64-unknown-elf \
// RUN: | FileCheck --check-prefix=CHECK-RV64FD %s
@@ -257,12 +257,12 @@
// CHECK-RV64FD: "-cc1" "-triple" "riscv64-unknown-unknown-elf"
// CHECK-RV64FD-SAME: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]"
// CHECK-RV64FD-SAME: "-isysroot" "[[SYSROOT:[^"]*]]"
-// CHECK-RV64FD-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}rv64imafdc{{[/\\]+}}lp64d{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}v1"
-// CHECk-RV64FD-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}rv64imafdc{{[/\\]+}}lp64d{{[/\\]+}}include"
+// CHECK-RV64FD-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}rv64imafdc_zicsr_zifencei{{[/\\]+}}lp64d{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}v1"
+// CHECk-RV64FD-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}rv64imafdc_zicsr_zifencei{{[/\\]+}}lp64d{{[/\\]+}}include"
// CHECK-RV64FD-SAME: "-x" "c++" "{{.*}}baremetal.cpp"
// CHECK-RV64FD-NEXT: ld{{(.exe)?}}" "{{.*}}.o" "-Bstatic"
-// CHECK-RV64FD-SAME: "-L[[SYSROOT:[^"]+]]{{[/\\]+}}rv64imafdc{{[/\\]+}}lp64d{{[/\\]+}}lib"
-// CHECK-RV64FD-SAME: "-L[[RESOURCE_DIR:[^"]+]]{{[/\\]+}}lib{{[/\\]+}}baremetal{{[/\\]+}}rv64imafdc{{[/\\]+}}lp64d"
+// CHECK-RV64FD-SAME: "-L[[SYSROOT:[^"]+]]{{[/\\]+}}rv64imafdc_zicsr_zifencei{{[/\\]+}}lp64d{{[/\\]+}}lib"
+// CHECK-RV64FD-SAME: "-L[[RESOURCE_DIR:[^"]+]]{{[/\\]+}}lib{{[/\\]+}}baremetal{{[/\\]+}}rv64imafdc_zicsr_zifencei{{[/\\]+}}lp64d"
// RUN: %clang %s -### 2>&1 --target=riscv32-unknown-elf \
// RUN: -march=rv32i -mabi=ilp32 \
@@ -319,11 +319,11 @@
// CHECK-RV32IAC-SAME: "-L[[SYSROOT:[^"]+]]{{[/\\]+}}rv32iac{{[/\\]+}}ilp32{{[/\\]+}}lib"
// CHECK-RV32IAC-SAME: "-L[[RESOURCE_DIR:[^"]+]]{{[/\\]+}}lib{{[/\\]+}}baremetal{{[/\\]+}}rv32iac{{[/\\]+}}ilp32"
-// RUN: %clang %s -### 2>&1 --target=riscv32-unknown-elf -march=rv32imafc -mabi=ilp32f \
+// RUN: %clang %s -### 2>&1 --target=riscv32-unknown-elf -march=rv32imafc_zicsr_zifencei -mabi=ilp32f \
// RUN: --sysroot=%S/Inputs/basic_riscv32_tree/riscv32-unknown-elf \
// RUN: | FileCheck --check-prefix=CHECK-RV32IMAFC %s
-// RUN: %clang %s -### 2>&1 --target=riscv32-unknown-elf -march=rv32imafdc -mabi=ilp32f \
+// RUN: %clang %s -### 2>&1 --target=riscv32-unknown-elf -march=rv32imafdc_zicsr_zifencei -mabi=ilp32f \
// RUN: --sysroot=%S/Inputs/basic_riscv32_tree/riscv32-unknown-elf \
// RUN: | FileCheck --check-prefix=CHECK-RV32IMAFC %s
@@ -334,12 +334,12 @@
// CHECK-RV32IMAFC: "-cc1" "-triple" "riscv32-unknown-unknown-elf"
// CHECK-RV32IMAFC-SAME: "-resource-dir" "[[RESOURCE_DIR:[^"]+]]"
// CHECK-RV32IMAFC-SAME: "-isysroot" "[[SYSROOT:[^"]*]]"
-// CHECK-RV32IMAFC-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}rv32imafc{{[/\\]+}}ilp32f{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}v1"
-// CHECK-RV32IMAFC-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}rv32imafc{{[/\\]+}}ilp32f{{[/\\]+}}include"
+// CHECK-RV32IMAFC-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}rv32imafc_zicsr_zifencei{{[/\\]+}}ilp32f{{[/\\]+}}include{{[/\\]+}}c++{{[/\\]+}}v1"
+// CHECK-RV32IMAFC-SAME: "-internal-isystem" "[[SYSROOT]]{{[/\\]+}}rv32imafc_zicsr_zifencei{{[/\\]+}}ilp32f{{[/\\]+}}include"
// CHECK-RV32IMAFC-SAME: "-x" "c++" "{{.*}}baremetal.cpp"
// CHECK-RV32IMAFC-NEXT: ld{{(.exe)?}}" "{{.*}}.o" "-Bstatic"
-// CHECK-RV32IMAFC-SAME: "-L[[SYSROOT:[^"]+]]{{[/\\]+}}rv32imafc{{[/\\]+}}ilp32f{{[/\\]+}}lib"
-// CHECK-RV32IMAFC-SAME: "-L[[RESOURCE_DIR:[^"]+]]{{[/\\]+}}lib{{[/\\]+}}baremetal{{[/\\]+}}rv32imafc{{[/\\]+}}ilp32f"
+// CHECK-RV32IMAFC-SAME: "-L[[SYSROOT:[^"]+]]{{[/\\]+}}rv32imafc_zicsr_zifencei{{[/\\]+}}ilp32f{{[/\\]+}}lib"
+// CHECK-RV32IMAFC-SAME: "-L[[RESOURCE_DIR:[^"]+]]{{[/\\]+}}lib{{[/\\]+}}baremetal{{[/\\]+}}rv32imafc_zicsr_zifencei{{[/\\]+}}ilp32f"
// Check that compiler-rt library without the arch filename suffix will
// be used if present.
Index: clang/lib/Driver/ToolChains/Gnu.cpp
===================================================================
--- clang/lib/Driver/ToolChains/Gnu.cpp
+++ clang/lib/Driver/ToolChains/Gnu.cpp
@@ -1721,8 +1721,14 @@
llvm::StringSet<> Added_ABIs;
StringRef ABIName = tools::riscv::getRISCVABI(Args, TargetTriple);
StringRef MArch = tools::riscv::getRISCVArch(Args, TargetTriple);
+ auto marchIsSubset = [](StringRef MArch, StringRef MultilibMarch) {
+ return (MArch == MultilibMarch) ||
+ MArch == (MultilibMarch + "_zicsr").str() ||
+ MArch == (MultilibMarch + "_zicsr_zifencei").str();
+ };
+
for (auto Element : RISCVMultilibSet) {
- addMultilibFlag(MArch == Element.march,
+ addMultilibFlag(marchIsSubset(MArch, Element.march),
Twine("march=", Element.march).str().c_str(), Flags);
if (!Added_ABIs.count(Element.mabi)) {
Added_ABIs.insert(Element.mabi);
Index: clang/lib/Driver/ToolChains/BareMetal.cpp
===================================================================
--- clang/lib/Driver/ToolChains/BareMetal.cpp
+++ clang/lib/Driver/ToolChains/BareMetal.cpp
@@ -41,16 +41,16 @@
if (TargetTriple.isRISCV64()) {
Multilib Imac = makeMultilib("").flag("+march=rv64imac").flag("+mabi=lp64");
- Multilib Imafdc = makeMultilib("/rv64imafdc/lp64d")
- .flag("+march=rv64imafdc")
+ Multilib Imafdc = makeMultilib("/rv64imafdc_zicsr_zifencei/lp64d")
+ .flag("+march=rv64imafdc_zicsr_zifencei")
.flag("+mabi=lp64d");
// Multilib reuse
- bool UseImafdc =
- (Arch == "rv64imafdc") || (Arch == "rv64gc"); // gc => imafdc
+ bool UseImafdc = (Arch == "rv64imafdc_zicsr_zifencei") ||
+ (Arch == "rv64gc"); // gc => imafdc
addMultilibFlag((Arch == "rv64imac"), "march=rv64imac", Flags);
- addMultilibFlag(UseImafdc, "march=rv64imafdc", Flags);
+ addMultilibFlag(UseImafdc, "march=rv64imafdc_zicsr_zifencei", Flags);
addMultilibFlag(Abi == "lp64", "mabi=lp64", Flags);
addMultilibFlag(Abi == "lp64d", "mabi=lp64d", Flags);
@@ -67,21 +67,22 @@
Multilib Iac = makeMultilib("/rv32iac/ilp32")
.flag("+march=rv32iac")
.flag("+mabi=ilp32");
- Multilib Imafc = makeMultilib("/rv32imafc/ilp32f")
- .flag("+march=rv32imafc")
+ Multilib Imafc = makeMultilib("/rv32imafc_zicsr_zifencei/ilp32f")
+ .flag("+march=rv32imafc_zicsr_zifencei")
.flag("+mabi=ilp32f");
// Multilib reuse
bool UseI = (Arch == "rv32i") || (Arch == "rv32ic"); // ic => i
bool UseIm = (Arch == "rv32im") || (Arch == "rv32imc"); // imc => im
- bool UseImafc = (Arch == "rv32imafc") || (Arch == "rv32imafdc") ||
+ bool UseImafc = (Arch == "rv32imafc_zicsr_zifencei") ||
+ (Arch == "rv32imafdc_zicsr_zifencei") ||
(Arch == "rv32gc"); // imafdc,gc => imafc
addMultilibFlag(UseI, "march=rv32i", Flags);
addMultilibFlag(UseIm, "march=rv32im", Flags);
addMultilibFlag((Arch == "rv32iac"), "march=rv32iac", Flags);
addMultilibFlag((Arch == "rv32imac"), "march=rv32imac", Flags);
- addMultilibFlag(UseImafc, "march=rv32imafc", Flags);
+ addMultilibFlag(UseImafc, "march=rv32imafc_zicsr_zifencei", Flags);
addMultilibFlag(Abi == "ilp32", "mabi=ilp32", Flags);
addMultilibFlag(Abi == "ilp32f", "mabi=ilp32f", Flags);
Index: clang/lib/Driver/ToolChains/Arch/RISCV.cpp
===================================================================
--- clang/lib/Driver/ToolChains/Arch/RISCV.cpp
+++ clang/lib/Driver/ToolChains/Arch/RISCV.cpp
@@ -280,11 +280,11 @@
StringRef MABI = A->getValue();
if (MABI.equals_insensitive("ilp32e"))
- return "rv32e";
+ return "rv32e_zicsr_zifencei";
else if (MABI.startswith_insensitive("ilp32"))
- return "rv32imafdc";
+ return "rv32imafdc_zicsr_zifencei";
else if (MABI.startswith_insensitive("lp64"))
- return "rv64imafdc";
+ return "rv64imafdc_zicsr_zifencei";
}
// 4. Choose a default based on the triple
@@ -294,14 +294,14 @@
// - On all other OSs we use `rv{XLEN}imafdc` (equivalent to `rv{XLEN}gc`)
if (Triple.isRISCV32()) {
if (Triple.getOS() == llvm::Triple::UnknownOS)
- return "rv32imac";
+ return "rv32imac_zicsr_zifencei";
else
- return "rv32imafdc";
+ return "rv32imafdc_zicsr_zifencei";
} else {
if (Triple.getOS() == llvm::Triple::UnknownOS)
- return "rv64imac";
+ return "rv64imac_zicsr_zifencei";
else
- return "rv64imafdc";
+ return "rv64imafdc_zicsr_zifencei";
}
}
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